Re: [PATCH 2/3] dt-bindings: power: mediatek: Update example to use phandle to syscon
From: Rob Herring
Date: Mon Jul 18 2022 - 14:07:00 EST
On Mon, Jul 11, 2022 at 02:25:02PM +0200, AngeloGioacchino Del Regno wrote:
> The preferred way of declaring this node is by using a phandle to
> syscon: update the example to reflect that.
Preferred by who? Not me.
What problem are you trying to solve? Better be a good reason for
breaking compatibility.
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
> ---
> .../power/mediatek,power-controller.yaml | 125 +++++++++---------
> 1 file changed, 63 insertions(+), 62 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> index 848fdff7c9d8..bed059e4401d 100644
> --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> @@ -237,76 +237,77 @@ examples:
> scpsys: syscon@10006000 {
> compatible = "syscon", "simple-mfd";
Only generic compatibles is certainly not preferred.
> reg = <0 0x10006000 0 0x1000>;
> + };
> + };
>
> - spm: power-controller {
> - compatible = "mediatek,mt8173-power-controller";
> + spm: power-controller {
> + compatible = "mediatek,mt8173-power-controller";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> + syscon = <&scpsys>;
> +
> + /* power domains of the SoC */
> + power-domain@MT8173_POWER_DOMAIN_VDEC {
> + reg = <MT8173_POWER_DOMAIN_VDEC>;
> + clocks = <&topckgen CLK_TOP_MM_SEL>;
> + clock-names = "mm";
> + #power-domain-cells = <0>;
> + };
> + power-domain@MT8173_POWER_DOMAIN_VENC {
> + reg = <MT8173_POWER_DOMAIN_VENC>;
> + clocks = <&topckgen CLK_TOP_MM_SEL>,
> + <&topckgen CLK_TOP_VENC_SEL>;
> + clock-names = "mm", "venc";
> + #power-domain-cells = <0>;
> + };
> + power-domain@MT8173_POWER_DOMAIN_ISP {
> + reg = <MT8173_POWER_DOMAIN_ISP>;
> + clocks = <&topckgen CLK_TOP_MM_SEL>;
> + clock-names = "mm";
> + #power-domain-cells = <0>;
> + };
> + power-domain@MT8173_POWER_DOMAIN_MM {
> + reg = <MT8173_POWER_DOMAIN_MM>;
> + clocks = <&topckgen CLK_TOP_MM_SEL>;
> + clock-names = "mm";
> + #power-domain-cells = <0>;
> + mediatek,infracfg = <&infracfg>;
> + };
> + power-domain@MT8173_POWER_DOMAIN_VENC_LT {
> + reg = <MT8173_POWER_DOMAIN_VENC_LT>;
> + clocks = <&topckgen CLK_TOP_MM_SEL>,
> + <&topckgen CLK_TOP_VENC_LT_SEL>;
> + clock-names = "mm", "venclt";
> + #power-domain-cells = <0>;
> + };
> + power-domain@MT8173_POWER_DOMAIN_AUDIO {
> + reg = <MT8173_POWER_DOMAIN_AUDIO>;
> + #power-domain-cells = <0>;
> + };
> + power-domain@MT8173_POWER_DOMAIN_USB {
> + reg = <MT8173_POWER_DOMAIN_USB>;
> + #power-domain-cells = <0>;
> + };
> + power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
> + reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
> + clocks = <&clk26m>;
> + clock-names = "mfg";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> +
> + power-domain@MT8173_POWER_DOMAIN_MFG_2D {
> + reg = <MT8173_POWER_DOMAIN_MFG_2D>;
> #address-cells = <1>;
> #size-cells = <0>;
> #power-domain-cells = <1>;
>
> - /* power domains of the SoC */
> - power-domain@MT8173_POWER_DOMAIN_VDEC {
> - reg = <MT8173_POWER_DOMAIN_VDEC>;
> - clocks = <&topckgen CLK_TOP_MM_SEL>;
> - clock-names = "mm";
> - #power-domain-cells = <0>;
> - };
> - power-domain@MT8173_POWER_DOMAIN_VENC {
> - reg = <MT8173_POWER_DOMAIN_VENC>;
> - clocks = <&topckgen CLK_TOP_MM_SEL>,
> - <&topckgen CLK_TOP_VENC_SEL>;
> - clock-names = "mm", "venc";
> - #power-domain-cells = <0>;
> - };
> - power-domain@MT8173_POWER_DOMAIN_ISP {
> - reg = <MT8173_POWER_DOMAIN_ISP>;
> - clocks = <&topckgen CLK_TOP_MM_SEL>;
> - clock-names = "mm";
> - #power-domain-cells = <0>;
> - };
> - power-domain@MT8173_POWER_DOMAIN_MM {
> - reg = <MT8173_POWER_DOMAIN_MM>;
> - clocks = <&topckgen CLK_TOP_MM_SEL>;
> - clock-names = "mm";
> + power-domain@MT8173_POWER_DOMAIN_MFG {
> + reg = <MT8173_POWER_DOMAIN_MFG>;
> #power-domain-cells = <0>;
> mediatek,infracfg = <&infracfg>;
> };
> - power-domain@MT8173_POWER_DOMAIN_VENC_LT {
> - reg = <MT8173_POWER_DOMAIN_VENC_LT>;
> - clocks = <&topckgen CLK_TOP_MM_SEL>,
> - <&topckgen CLK_TOP_VENC_LT_SEL>;
> - clock-names = "mm", "venclt";
> - #power-domain-cells = <0>;
> - };
> - power-domain@MT8173_POWER_DOMAIN_AUDIO {
> - reg = <MT8173_POWER_DOMAIN_AUDIO>;
> - #power-domain-cells = <0>;
> - };
> - power-domain@MT8173_POWER_DOMAIN_USB {
> - reg = <MT8173_POWER_DOMAIN_USB>;
> - #power-domain-cells = <0>;
> - };
> - power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
> - reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
> - clocks = <&clk26m>;
> - clock-names = "mfg";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - #power-domain-cells = <1>;
> -
> - power-domain@MT8173_POWER_DOMAIN_MFG_2D {
> - reg = <MT8173_POWER_DOMAIN_MFG_2D>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - #power-domain-cells = <1>;
> -
> - power-domain@MT8173_POWER_DOMAIN_MFG {
> - reg = <MT8173_POWER_DOMAIN_MFG>;
> - #power-domain-cells = <0>;
> - mediatek,infracfg = <&infracfg>;
> - };
> - };
> - };
> };
> };
> };
> --
> 2.35.1
>
>