Re: [RFC Patch net-next 04/10] net: dsa: microchip: add common duplex and flow control function

[Arun.Ramadoss]

On Tue, 2022-07-19 at 13:52 +0300, Vladimir Oltean wrote:
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> On Tue, Jul 12, 2022 at 09:33:02PM +0530, Arun Ramadoss wrote:
> > This patch add common function for configuring the Full/Half duplex
> > and
> > transmit/receive flow control. KSZ8795 uses the Global control
> > register
> > 4 for configuring the duplex and flow control, whereas all other
> > KSZ9477
> > based switch uses the xMII Control 0 register.
> > 
> > Signed-off-by: Arun Ramadoss <arun.ramadoss@xxxxxxxxxxxxx>
> > ---
> >  drivers/net/dsa/microchip/ksz9477_reg.h  |  1 -
> >  drivers/net/dsa/microchip/ksz_common.c   | 64
> > ++++++++++++++++++++++++
> >  drivers/net/dsa/microchip/ksz_common.h   |  8 +++
> >  drivers/net/dsa/microchip/lan937x_main.c | 24 +++------
> >  drivers/net/dsa/microchip/lan937x_reg.h  |  3 --
> >  5 files changed, 80 insertions(+), 20 deletions(-)
> > 
> > diff --git a/drivers/net/dsa/microchip/ksz9477_reg.h
> > b/drivers/net/dsa/microchip/ksz9477_reg.h
> > index 2649fdf0bae1..6ca859345932 100644
> > --- a/drivers/net/dsa/microchip/ksz9477_reg.h
> > +++ b/drivers/net/dsa/microchip/ksz9477_reg.h
> > @@ -1178,7 +1178,6 @@
> >  #define REG_PORT_XMII_CTRL_0         0x0300
> > 
> >  #define PORT_SGMII_SEL                       BIT(7)
> > -#define PORT_MII_FULL_DUPLEX         BIT(6)
> >  #define PORT_GRXC_ENABLE             BIT(0)
> > 
> >  #define REG_PORT_XMII_CTRL_1         0x0301
> > diff --git a/drivers/net/dsa/microchip/ksz_common.c
> > b/drivers/net/dsa/microchip/ksz_common.c
> > index f41cd2801210..4ef0ee9a245d 100644
> > --- a/drivers/net/dsa/microchip/ksz_common.c
> > +++ b/drivers/net/dsa/microchip/ksz_common.c
> > @@ -280,6 +280,8 @@ static const u32 ksz8795_masks[] = {
> >       [DYNAMIC_MAC_TABLE_FID]         = GENMASK(26, 20),
> >       [DYNAMIC_MAC_TABLE_SRC_PORT]    = GENMASK(26, 24),
> >       [DYNAMIC_MAC_TABLE_TIMESTAMP]   = GENMASK(28, 27),
> > +     [P_MII_TX_FLOW_CTRL]            = BIT(5),
> > +     [P_MII_RX_FLOW_CTRL]            = BIT(5),
> 
> The masks are the same for TX and RX flow control and the writes are
> to
> the same register (regs[P_XMII_CTRL_0]), is this an error?

I have gone through ksz8795 datasheet, I could not find separate bit
for Tx and Rx flow control bit. Bit 5 mentioned as Flow control on the
switch MII/RMII interface. So I had configured same bit for Tx and Rx.

> 
> >  };
> > 
> >  static const u8 ksz8795_values[] = {
> > @@ -287,6 +289,8 @@ static const u8 ksz8795_values[] = {
> >       [P_MII_NOT_1GBIT]               = 0,
> >       [P_MII_100MBIT]                 = 0,
> >       [P_MII_10MBIT]                  = 1,
> > +     [P_MII_FULL_DUPLEX]             = 0,
> > +     [P_MII_HALF_DUPLEX]             = 1,
> >  };
> > 
> >  static const u8 ksz8795_shifts[] = {
> > @@ -366,6 +370,8 @@ static const u16 ksz9477_regs[] = {
> >  static const u32 ksz9477_masks[] = {
> >       [ALU_STAT_WRITE]                = 0,
> >       [ALU_STAT_READ]                 = 1,
> > +     [P_MII_TX_FLOW_CTRL]            = BIT(5),
> > +     [P_MII_RX_FLOW_CTRL]            = BIT(3),
> >  };
> > 
> > --
> > 2.36.1
> > 
> 
>