Re: [PATCH] KVM: SVM: Do not virtualize MSR accesses for APIC LVTT register

[Paolo Bonzini]

On 7/25/22 05:34, Suravee Suthikulpanit wrote:
> AMD does not support APIC TSC-deadline timer mode. AVIC hardware
> will generate GP fault when guest kernel writes 1 to bits [18]
> of the APIC LVTT register (offset 0x32) to set the timer mode.
> (Note: bit 18 is reserved on AMD system).
>
> Therefore, always intercept and let KVM emulate the MSR accesses.
>
> Fixes: f3d7c8aa6882 ("KVM: SVM: Fix x2APIC MSRs interception")
> Signed-off-by: Suravee Suthikulpanit<suravee.suthikulpanit@xxxxxxx>

Does this fix some kvm-unit-tests testcase?

Anyway, I queued the patch, thanks!

Paolo