[ EXTERNAL EMAIL ]It's fine with me. It's mainly Jerome's opinion.
On 28/07/2022 07:42, Yu Tu wrote:
Add new clock controller compatible and dt-bindings header for the
Everything-Else domain of the S4 SoC.
Signed-off-by: Yu Tu <yu.tu@xxxxxxxxxxx>
diff --git a/MAINTAINERS b/MAINTAINERS
index c1abc53f9e91..f872d0c0c253 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1775,6 +1775,7 @@ F: Documentation/devicetree/bindings/clock/amlogic*
F: drivers/clk/meson/
F: include/dt-bindings/clock/gxbb*
F: include/dt-bindings/clock/meson*
+F: include/dt-bindings/clock/s4-clkc.h
ARM/Amlogic Meson SoC Crypto Drivers
M: Corentin Labbe <clabbe@xxxxxxxxxxxx>
diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
new file mode 100644
index 000000000000..b686c8877419
--- /dev/null
+++ b/include/dt-bindings/clock/s4-clkc.h
Filename with vendor prefix, so:
amlogic,s4-clkc.h
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
+ * Author: Yu Tu <yu.tu@xxxxxxxxxxx>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H
+#define _DT_BINDINGS_CLOCK_S4_CLKC_H
+
+/*
+ * CLKID index values
+ */
+
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2 3
+#define CLKID_FCLK_DIV3 5
+#define CLKID_FCLK_DIV4 7
+#define CLKID_FCLK_DIV5 9
+#define CLKID_FCLK_DIV7 11
Why these aren't continuous? IDs are expected to be incremented by 1.
+
+#endif /* _DT_BINDINGS_CLOCK_S4_CLKC_H */
Best regards,
Krzysztof
.