Re: [PATCH 7/8] drm/tidss: Fix clock request value for OLDI videoports

[Aradhya Bhatia]

On 28-Jul-22 15:35, Tomi Valkeinen wrote:
> On 19/07/2022 11:08, Aradhya Bhatia wrote:
> > The OLDI TX(es) require a serial clock which is 7 times the pixel clock
> > of the display panel. When the OLDI is enabled in DSS, the pixel clock
> > input of the corresponding videoport gets a divided-by 7 value of the
> > requested clock.
> >
> > For the am625-dss, the requested clock needs to be 7 times the value.
> >
> > Update the clock frequency by requesting 7 times the value.
> >
> > Signed-off-by: Aradhya Bhatia <a-bhatia1@xxxxxx>
> > ---
> >   drivers/gpu/drm/tidss/tidss_dispc.c | 10 ++++++++++
> >   1 file changed, 10 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c 
> > b/drivers/gpu/drm/tidss/tidss_dispc.c
> > index c4a5f808648f..0b9689453ee8 100644
> > --- a/drivers/gpu/drm/tidss/tidss_dispc.c
> > +++ b/drivers/gpu/drm/tidss/tidss_dispc.c
> > @@ -1326,6 +1326,16 @@ int dispc_vp_set_clk_rate(struct dispc_device 
> > *dispc, u32 hw_videoport,
> >       int r;
> >       unsigned long new_rate;
> > +    /*
> > +     * For AM625 OLDI video ports, the requested pixel clock needs to 
> > take into account the
> > +     * serial clock required for the serialization of DPI signals 
> > into LVDS signals. The
> > +     * incoming pixel clock on the OLDI video port gets divided by 7 
> > whenever OLDI enable bit
> > +     * gets set.
> > +     */
> > +    if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI &&
> > +        dispc->feat->subrev == DISPC_AM625)
> > +        rate *= 7;
> > +
> >       r = clk_set_rate(dispc->vp_clk[hw_videoport], rate);
> >       if (r) {
> >           dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n",
>
> The AM625 TRM seems to be missing the "DSS integration" section, even if 
> it's referred to in three places in the TRM. Supposedly that has details 
> about the clocking.
>
> Shouldn't the source clock be 3.5x when dual-link mode is used?
There should not be.

Whenever OLDI is enabled, the clock generated from the PLL is 7 times
the required pixel clock.

For the OLDI TXes, the clock passes through a /2 divider. This divider
only gets activated when the dual mode has been enabled in the OLDI
configuration. Thus the OLDI TXes get 3.5x the pixel clock in dual mode.

When the OLDI has been configured for a single mode,
the PLL clock passes through the /2 divider without any change.

> While I don't know the details, this doesn't feel correct. We're 
> supposed to be setting the VP pixel clock here, and the serial clock 
> would be derived from that as it's done on AM65x. Is the DT clock tree
> wrong for AM625?
Ideally, yes, its the pixel frequency that we are supposed to set here.

The same PLL clock (7 times the pixel frequency) passes through a /7
clock divider. This clock divider only gets active when OLDI is enabled.
Thus, the DSS VP clock input, only gets the actual pixel frequency that
it needs.

Since, the /7 divider is controlled by a signal from the DSS, the driver
needs to request 7 times more the pixel clock to accommodate for the
divider.

In AM65X, the system FW is able to model the 7 times requirement because
the divider is not controlled by the DSS signal. DSS signal controls a
multiplexer which receives both PLL Clock and PLL / 7 clock.


Regards
Aradhya