Re: [PATCH v16 3/8] drm/mediatek: Add MT8195 Embedded DisplayPort driver

[CK Hu]

Hi. Bo-Chen:

On Fri, 2022-08-05 at 18:14 +0800, Bo-Chen Chen wrote:
> From: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
> 
> This patch adds a embedded displayport driver for the MediaTek mt8195
> SoC.
> 
> It supports the MT8195, the embedded DisplayPort units. It offers
> DisplayPort 1.4 with up to 4 lanes.
> 
> The driver creates a child device for the phy. The child device will
> never exist without the parent being active. As they are sharing a
> register range, the parent passes a regmap pointer to the child so
> that
> both can work with the same register range. The phy driver sets
> device
> data that is read by the parent to get the phy device that can be
> used
> to control the phy properties.
> 
> This driver is based on an initial version by
> Jitao shi <jitao.shi@xxxxxxxxxxxx>
> 
> Signed-off-by: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
> Signed-off-by: Guillaume Ranquet <granquet@xxxxxxxxxxxx>
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@xxxxxxxxxxxx>
> Tested-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@xxxxxxxxxxxxx>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@xxxxxxxxxxxxx>
> ---

[snip]

> +
> +static int mtk_dp_parse_capabilities(struct mtk_dp *mtk_dp)
> +{
> +	u8 val;
> +	ssize_t ret;
> +	struct mtk_dp_train_info *train_info = &mtk_dp->train_info;
> +
> +	drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER,
> DP_SET_POWER_D0);
> +	usleep_range(2000, 5000);
> +
> +	drm_dp_read_dpcd_caps(&mtk_dp->aux, mtk_dp->rx_cap);
> +
> +	train_info->link_rate = min_t(int, mtk_dp->max_linkrate,
> +				      drm_dp_max_link_rate(mtk_dp-
> >rx_cap));
> +	train_info->lane_count = min_t(int, mtk_dp->max_lanes,
> +				       drm_dp_max_lane_count(mtk_dp-
> >rx_cap));
> +
> +	train_info->tps3 = drm_dp_tps3_supported(mtk_dp->rx_cap);
> +	train_info->tps4 = drm_dp_tps4_supported(mtk_dp->rx_cap);

You could drop tps3, tps4 and add channel_eq_pattern like this:

if (drm_dp_tps4_supported(mtk_dp->rx_cap))
	train_info->channel_eq_pattern = DP_TRAINING_PATTERN_4;
else if (drm_dp_tps4_supported(mtk_dp->rx_cap))
	train_info->channel_eq_pattern = DP_TRAINING_PATTERN_3;
else
	train_info->channel_eq_pattern = DP_TRAINING_PATTERN_2;

Regards,
CK

> +
> +	train_info->sink_ssc = drm_dp_max_downspread(mtk_dp->rx_cap);
> +
> +	ret = drm_dp_dpcd_readb(&mtk_dp->aux, DP_MSTM_CAP, &val);
> +	if (ret < 1) {
> +		drm_err(mtk_dp->drm_dev, "Read mstm cap failed\n");
> +		return ret == 0 ? -EIO : ret;
> +	}
> +
> +	if (val & DP_MST_CAP) {
> +		/* Clear DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 */
> +		ret = drm_dp_dpcd_readb(&mtk_dp->aux,
> +					DP_DEVICE_SERVICE_IRQ_VECTOR_ES
> I0,
> +					&val);
> +		if (ret < 1) {
> +			drm_err(mtk_dp->drm_dev, "Read irq vector
> failed\n");
> +			return ret == 0 ? -EIO : ret;
> +		}
> +
> +		if (val)
> +			drm_dp_dpcd_writeb(&mtk_dp->aux,
> +					   DP_DEVICE_SERVICE_IRQ_VECTOR
> _ESI0,
> +					   val);
> +	}
> +
> +	return 0;
> +}
> +