Re: [PATCH 1/2] dt-bindings: clock: Add Qualcomm SC8280XP display clock bindings

[Krzysztof Kozlowski]

On 11/08/2022 07:12, Bjorn Andersson wrote:
> The Qualcomm SC8280XP platform has two display clock controllers, add a
> binding for these.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
> ---
>  .../bindings/clock/qcom,dispcc-sc8280xp.yaml  |  98 +++++++++++++++++
>  .../dt-bindings/clock/qcom,dispcc-sc8280xp.h  | 100 ++++++++++++++++++
>  2 files changed, 198 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml
>  create mode 100644 include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml
> new file mode 100644
> index 000000000000..98e5dfd53f76
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml
> @@ -0,0 +1,98 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display Clock & Reset Controller Binding for SC8280XP
> +
> +maintainers:
> +  - Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
> +
> +description: |
> +  Qualcomm display clock control module which supports the clocks, resets and
> +  power domains for the two MDSS instances on SC8280XP.
> +
> +  See also:
> +    include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,sc8280x-dispcc0
> +      - qcom,sc8280x-dispcc1

These are two independent and different devices, right? Driver seems to
confirm this which would justify using indexes in compatible.

> +
> +  clocks:
> +    items:
> +      - description: AHB interface clock,
> +      - description: SoC CXO clock
> +      - description: SoC sleep clock
> +      - description: DisplayPort 0 link clock
> +      - description: DisplayPort 0 VCO div clock
> +      - description: DisplayPort 1 link clock
> +      - description: DisplayPort 1 VCO div clock
> +      - description: DisplayPort 2 link clock
> +      - description: DisplayPort 2 VCO div clock
> +      - description: DisplayPort 3 link clock
> +      - description: DisplayPort 3 VCO div clock
> +      - description: DSI 0 PLL byte clock
> +      - description: DSI 0 PLL DSI clock
> +      - description: DSI 1 PLL byte clock
> +      - description: DSI 1 PLL DSI clock
> +
> +  '#clock-cells':
> +    const: 1
> +
> +  '#reset-cells':
> +    const: 1
> +
> +  '#power-domain-cells':
> +    const: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +  power-domains:
> +    description:
> +      A phandle and PM domain specifier for the MMCX power domain.
> +    maxItems: 1

Three lines can be shorter:

items:
 - description: MMCX power domain

With above:

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>


Best regards,
Krzysztof