Re: [PATCH] perf: riscv: fix broken build due to struct redefinition

[Palmer Dabbelt]

On Fri, 12 Aug 2022 07:19:54 PDT (-0700), Conor.Dooley@xxxxxxxxxxxxx wrote:
> On 12/08/2022 15:13, Jessica Clarke wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On 12 Aug 2022, at 14:51, Conor Dooley <conor.dooley@xxxxxxxxxxxxx> wrote:
> > > Building riscv/for-next produces following error:
> > > drivers/perf/riscv_pmu_sbi.c:44:7: error: redefinition of 'sbi_pmu_ctr_info'
> > > union sbi_pmu_ctr_info {
> > >       ^
> > > arch/riscv/include/asm/sbi.h:125:7: note: previous definition is here
> > > union sbi_pmu_ctr_info {
> > >
> > > This appears to have been caused by a merge conflict resolution between
> > > riscv/for-next & riscv/fixes, causing the struct define not being
> >
> > union, not struct
>
> autopilot, thanks :)
>
> > Jess
> >
> > > properly moved to its header.
> > >
> > > Fixes: 9a7ccac63f9c ("perf: riscv_pmu{,_sbi}: Miscallenous improvement & fixes")
> > > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> > > ---
> > > drivers/perf/riscv_pmu_sbi.c | 14 --------------
> > > 1 file changed, 14 deletions(-)
> > >
> > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> > > index e7c6fecbf061..6f6681bbfd36 100644
> > > --- a/drivers/perf/riscv_pmu_sbi.c
> > > +++ b/drivers/perf/riscv_pmu_sbi.c
> > > @@ -41,20 +41,6 @@ static const struct attribute_group *riscv_pmu_attr_groups[] = {
> > >        NULL,
> > > };
> > >
> > > -union sbi_pmu_ctr_info {
> > > -     unsigned long value;
> > > -     struct {
> > > -             unsigned long csr:12;
> > > -             unsigned long width:6;
> > > -#if __riscv_xlen == 32
> > > -             unsigned long reserved:13;
> > > -#else
> > > -             unsigned long reserved:45;
> > > -#endif
> > > -             unsigned long type:1;
> > > -     };
> > > -};
> > > -
> > > /*
> > >   * RISC-V doesn't have hetergenous harts yet. This need to be part of
> > >   * per_cpu in case of harts with different pmu counters

Atish just poked me about this as I was tagging my PR, I squashed it in.  
I don't see a message on lore, not sure if something went off the rails 
or if it's just in the outbox on my box at home.