Re: Debugging a TTY race condition on M1 (memory ordering dragons)

[Peter Zijlstra]

On Mon, Aug 15, 2022 at 02:47:11PM +0100, Will Deacon wrote:

> > Behind the scenes, the work pending flag is atomically set with
> > test_and_set_bit() by queue_work_on(). That compiles down to my old
> > friend LDSETAL, which I already showed [2] does not provide the
> > guarantees test_and_set_bit() claims to have (== full memory barrier).
> > However, I can't get that litmus test to fail on real hardware, so that
> > may be a red herring as far as this bug goes.
> 
> As I mentioned in the thread you linked to, the architecture was undergoing
> review in this area. I should've followed back up, but in the end it was
> tightened retrospectively to provide the behaviour you wanted. This was
> achieved by augmenting the barrier-ordered-before relation with:
> 
>   * RW1 is a memory write effect W1 and is generated by an atomic instruction
>     with both Acquire and Release semantics.
> 
> You can see this in the latest Arm ARM.
> 
> However, test_and_set_bit() is unordered on failure (i.e. when the bit is
> unchanged) and uses READ_ONCE() as a quick check before the RmW. See the
> "ORDERING" section of Documentation/atomic_bitops.txt.

Damn, I forgot that too... :/

> I think you're missing the "shortcut" in test_and_set_bit():
> 
>         if (READ_ONCE(*p) & mask)
>                 return 1;
> 
>         old = arch_atomic_long_fetch_or(mask, (atomic_long_t *)p);
> 
> so if the bit is already set (which I think is the 'ret == false' case)
> then you've only got a control dependency here and we elide writing to
> B.

Given all that, I think workqueue wants to be fixed, it really does seem
to rely on full ordering for it's test_and_set_bit() usage.