[PATCH v9,2/7] dt-bindings: thermal: Add dt-binding document for LVTS thermal controllers

[bchihi]

From: Alexandre Bailon <abailon@xxxxxxxxxxxx>

Add dt-binding document for mt8192 and mt8195 LVTS thermal controllers.

Signed-off-by: Alexandre Bailon <abailon@xxxxxxxxxxxx>
Co-developed-by: Balsam CHIHI <bchihi@xxxxxxxxxxxx>
Signed-off-by: Balsam CHIHI <bchihi@xxxxxxxxxxxx>
---
 .../thermal/mediatek,lvts-thermal.yaml        | 152 ++++++++++++++++++
 1 file changed, 152 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml

diff --git a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml
new file mode 100644
index 000000000000..31d9e220513a
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml
@@ -0,0 +1,152 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek SoC LVTS thermal controller
+
+maintainers:
+  - Yu-Chia Chang <ethan.chang@xxxxxxxxxxxx>
+  - Ben Tseng <ben.tseng@xxxxxxxxxxxx>
+
+description: |
+  LVTS (Low Voltage Thermal Sensor).
+  The architecture will be first used on mt8192 and mt8195.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt8192-lvts-ap
+      - mediatek,mt8192-lvts-mcu
+      - mediatek,mt8195-lvts-ap
+      - mediatek,mt8195-lvts-mcu
+
+  "#thermal-sensor-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+    description: LVTS instance registers.
+
+  interrupts:
+    maxItems: 1
+    description: LVTS instance interrupts.
+
+  clocks:
+    maxItems: 1
+    description: LVTS instance clock.
+
+  resets:
+    maxItems: 1
+    description: |
+      LVTS instance SW reset for HW AP/MCU domain to clean temporary data
+      on HW initialization/resume.
+
+  nvmem-cells:
+    minItems: 1
+    maxItems: 2
+    description: Calibration efuse data for LVTS
+
+  nvmem-cell-names:
+    minItems: 1
+    maxItems: 2
+    description: Calibration efuse cell names for LVTS
+
+allOf:
+  - $ref: thermal-sensor.yaml#
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - mediatek,mt8192-lvts-ap
+              - mediatek,mt8192-lvts-mcu
+    then:
+      properties:
+        nvmem-cells:
+          items:
+            - description: Calibration efuse data for LVTS
+
+        nvmem-cell-names:
+          items:
+            - const: lvts_calib_data1
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - mediatek,mt8195-lvts-ap
+              - mediatek,mt8195-lvts-mcu
+    then:
+      properties:
+        nvmem-cells:
+          items:
+            - description: Calibration efuse data 1 for LVTS
+            - description: Calibration efuse data 2 for LVTS
+
+        nvmem-cell-names:
+          items:
+            - const: lvts_calib_data1
+            - const: lvts_calib_data2
+
+required:
+  - compatible
+  - '#thermal-sensor-cells'
+  - reg
+  - interrupts
+  - clocks
+  - resets
+  - nvmem-cells
+  - nvmem-cell-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8192-clk.h>
+    #include <dt-bindings/reset/mt8192-resets.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      lvts_ap: thermal-sensor@1100b000 {
+        compatible = "mediatek,mt8192-lvts-ap";
+        #thermal-sensor-cells = <1>;
+        reg = <0 0x1100b000 0 0x1000>;
+        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
+        clocks = <&infracfg CLK_INFRA_THERM>;
+        resets = <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>;
+        nvmem-cells = <&lvts_e_data1>;
+        nvmem-cell-names = "lvts_calib_data1";
+      };
+
+      lvts_mcu: thermal-sensor@11278000 {
+        compatible = "mediatek,mt8192-lvts-mcu";
+        #thermal-sensor-cells = <1>;
+        reg = <0 0x11278000 0 0x1000>;
+        interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
+        clocks = <&infracfg CLK_INFRA_THERM>;
+        resets = <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
+        nvmem-cells = <&lvts_e_data1>;
+        nvmem-cell-names = "lvts_calib_data1";
+      };
+    };
+
+    thermal_zones: thermal-zones {
+      cpu0-thermal {
+        polling-delay = <0>;
+        polling-delay-passive = <0>;
+        thermal-sensors = <&lvts_mcu 0>;
+      };
+
+      vpu1-thermal {
+        polling-delay = <0>;
+        polling-delay-passive = <0>;
+        thermal-sensors = <&lvts_ap 0>;
+      };
+    };
-- 
2.34.1