Re: [RESEND PATCH] perf/x86/intel: Fix unchecked MSR access error for Alder Lake N

[Sean Christopherson]

On Mon, Aug 22, 2022, Peter Zijlstra wrote:
> On Mon, Aug 22, 2022 at 05:08:55PM +0200, Andi Kleen wrote:
> > 
> > > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> > > index 2db93498ff71..232e24324fd7 100644
> > > --- a/arch/x86/events/intel/core.c
> > > +++ b/arch/x86/events/intel/core.c
> > > @@ -4473,6 +4473,11 @@ static bool init_hybrid_pmu(int cpu)
> > >   	struct x86_hybrid_pmu *pmu = NULL;
> > >   	int i;
> > > +	if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
> > > +		pr_warn_once("hybrid PMU and virt are incompatible\n");
> > > +		return false;
> > > +	}
> > 
> > It's totally possible to virtualize hybrid correctly, so I don't think this
> > is justified
> 
> With a magic incantation and a sacrificial chicken sure,

Pretty sure this one requires at least a goat.

> but the typical guest will not have it set up right and we'll get the kernel
> doing *splat*.

I 100% agree that typical VMMs will not get this right, but at the same time I
think this is firmly a host _kernel_ bug.

Checking X86_FEATURE_HYPERVISOR in the guest won't handle things like trying to
run a non-hyrbid vCPU model on a hybrid CPU, because IIUC, the "is_hybrid()" is
purely based on FMS, i.e. will be false if someone enumerates a big core vCPU on
a hybrid CPU.

So until KVM gets sane handling, shouldn't this be?

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index f969410d0c90..0a8accfc3018 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -2999,12 +2999,8 @@ void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
        }

        cap->version            = x86_pmu.version;
-       /*
-        * KVM doesn't support the hybrid PMU yet.
-        * Return the common value in global x86_pmu,
-        * which available for all cores.
-        */
-       cap->num_counters_gp    = x86_pmu.num_counters;
+       /* KVM doesn't support the hybrid PMU yet. */
+       cap->num_counters_gp    = is_hybrid() ? 0 : x86_pmu.num_counters;
        cap->num_counters_fixed = x86_pmu.num_counters_fixed;
        cap->bit_width_gp       = x86_pmu.cntval_bits;
        cap->bit_width_fixed    = x86_pmu.cntval_bits;