RE: [EXT] Re: [PATCH v7 3/4] dt-bindings: irqchip: imx mu work as msi controller

From: Frank Li
Date: Thu Aug 25 2022 - 17:42:47 EST



> -----Original Message-----
> From: Rob Herring <robh@xxxxxxxxxx>
> Sent: Thursday, August 25, 2022 4:22 PM
> To: Frank Li <frank.li@xxxxxxx>
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> Subject: [EXT] Re: [PATCH v7 3/4] dt-bindings: irqchip: imx mu work as msi
> controller
>
> Caution: EXT Email
>
> On Mon, Aug 22, 2022 at 10:51:29AM -0500, Frank Li wrote:
> > I.MX mu support generate irq by write a register. Provide msi controller
> > support so other driver such as PCI EP can use it by standard msi
> > interface as doorbell.
> >
> > Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
> > ---
> > .../interrupt-controller/fsl,mu-msi.yaml | 98 +++++++++++++++++++
> > 1 file changed, 98 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/interrupt-
> controller/fsl,mu-msi.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-
> msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-
> msi.yaml
> > new file mode 100644
> > index 0000000000000..ac07b138e24c0
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-
> msi.yaml
> > @@ -0,0 +1,98 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicet
> ree.org%2Fschemas%2Finterrupt-controller%2Ffsl%2Cmu-
> msi.yaml%23&amp;data=05%7C01%7CFrank.Li%40nxp.com%7Cbff8f186128d
> 44209f4108da86dfc975%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
> %7C637970592959950791%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLj
> AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%
> 7C%7C&amp;sdata=DHCOhmaJAhwb8Gl%2FEbPj32B6lR2zcIvyMY%2BTuPACb
> zI%3D&amp;reserved=0
> > +$schema:
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicet
> ree.org%2Fmeta-
> schemas%2Fcore.yaml%23&amp;data=05%7C01%7CFrank.Li%40nxp.com%7
> Cbff8f186128d44209f4108da86dfc975%7C686ea1d3bc2b4c6fa92cd99c5c3016
> 35%7C0%7C0%7C637970592959950791%7CUnknown%7CTWFpbGZsb3d8eyJ
> WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> 7C3000%7C%7C%7C&amp;sdata=J4znEXyHnMyQOssSUsoxE2Mlhe2qCDC%2F
> 9WN6SKv69aM%3D&amp;reserved=0
> > +
> > +title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
> > +
> > +maintainers:
> > + - Frank Li <Frank.Li@xxxxxxx>
> > +
> > +description: |
> > + The Messaging Unit module enables two processors within the SoC to
> > + communicate and coordinate by passing messages (e.g. data, status
> > + and control) through the MU interface. The MU also provides the ability
> > + for one processor (A side) to signal the other processor (B side) using
> > + interrupts.
> > +
> > + Because the MU manages the messaging between processors, the MU
> uses
> > + different clocks (from each side of the different peripheral buses).
> > + Therefore, the MU must synchronize the accesses from one side to the
> > + other. The MU accomplishes synchronization using two sets of matching
> > + registers (Processor A-facing, Processor B-facing).
> > +
> > + MU can work as msi interrupt controller to do doorbell
> > +
> > +allOf:
> > + - $ref: /schemas/interrupt-controller/msi-controller.yaml#
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - fsl,imx6sx-mu-msi
> > + - fsl,imx7ulp-mu-msi
> > + - fsl,imx8ulp-mu-msi
> > + - fsl,imx8ulp-mu-msi-s4
> > +
> > + reg:
> > + items:
> > + - description: a side register base address
> > + - description: b side register base address
> > +
> > + reg-names:
> > + items:
> > + - const: processor a-facing
> > + - const: processor b-facing
>
> Isn't 'a' and 'b' sufficient to distinguish? Personally, doesn't really
> look like a case that benefits from -names at all.
>
> In any case, -names shouldn't have spaces.

I like "a" and "b".

But Marc Zyngier suggested use above name.
https://www.spinics.net/lists/linux-pci/msg128783.html

@Marc Zyngier

best regards
Frank Li

>
> > +
> > + interrupts:
> > + description: a side interrupt number.
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + power-domains:
> > + items:
> > + - description: a side power domain
> > + - description: b side power domain
> > +
> > + power-domain-names:
> > + items:
> > + - const: processor a-facing
> > + - const: processor b-facing
>
> Same here.
>
> > +
> > + interrupt-controller: true
> > +
> > + msi-controller: true
> > +
> > + "#msi-cells":
> > + const: 0
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - interrupt-controller
> > + - msi-controller
>
> #msi-cells should be required.
>
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/firmware/imx/rsrc.h>
> > +
> > + msi-controller@5d270000 {
> > + compatible = "fsl,imx6sx-mu-msi";
> > + msi-controller;
> > + #msi-cells = <0>;
> > + interrupt-controller;
> > + reg = <0x5d270000 0x10000>, /* A side */
> > + <0x5d300000 0x10000>; /* B side */
> > + reg-names = "processor a-facing", "processor b-facing";
> > + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
> > + power-domains = <&pd IMX_SC_R_MU_12A>,
> > + <&pd IMX_SC_R_MU_12B>;
> > + power-domain-names = "processor a-facing", "processor b-facing";
> > + };
> > --
> > 2.35.1
> >
> >