Re: [PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

[Rob Herring]

On Tue, Aug 30, 2022 at 3:36 AM Ben Dooks <ben.dooks@xxxxxxxxxx> wrote:
>
> With newer cores such as the p550, the SiFive composable cache can be
> a level 3 cache. Update the cache level to be one of 2 or 3.
>
> Signed-off-by: Ben Dooks <ben.dooks@xxxxxxxxxx>
> ---
>  Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Please send DT patches to the DT list. Resend so checks run.

Rob