Re: [PATCH] riscv/kprobe: Optimize the performance of patching instruction slot

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On Thu, 8 Sep 2022 01:21:27 +0800
Jisheng Zhang <jszhang@xxxxxxxxxx> wrote:

> On Wed, Sep 07, 2022 at 10:33:27AM +0800, Liao Chang wrote:
> > Since no race condition occurs on each instruction slot, hence it is
> > safe to patch instruction slot without stopping machine.
> 
> hmm, IMHO there's race when arming kprobe under SMP, so stopping
> machine is necessary here. Maybe I misundertand something.

Yeah, usually the self modifying code needs stop other CPUs some known
points so that other CPUs does not execute the instruction which will
be modified.
Even if a chip ensures that, is that safe for other implementations?
(Does RISC-V specification guarantee this behavior?)

Thank you,

> 
> > 
> > Signed-off-by: Liao Chang <liaochang1@xxxxxxxxxx>
> > ---
> >  arch/riscv/kernel/probes/kprobes.c | 8 +++++---
> >  1 file changed, 5 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/riscv/kernel/probes/kprobes.c b/arch/riscv/kernel/probes/kprobes.c
> > index e6e950b7cf32..eff7d7fab535 100644
> > --- a/arch/riscv/kernel/probes/kprobes.c
> > +++ b/arch/riscv/kernel/probes/kprobes.c
> > @@ -24,12 +24,14 @@ post_kprobe_handler(struct kprobe *, struct kprobe_ctlblk *, struct pt_regs *);
> >  static void __kprobes arch_prepare_ss_slot(struct kprobe *p)
> >  {
> >  	unsigned long offset = GET_INSN_LENGTH(p->opcode);
> > +	const kprobe_opcode_t brk_insn = __BUG_INSN_32;
> > +	kprobe_opcode_t slot[MAX_INSN_SIZE];
> >  
> >  	p->ainsn.api.restore = (unsigned long)p->addr + offset;
> >  
> > -	patch_text(p->ainsn.api.insn, p->opcode);
> > -	patch_text((void *)((unsigned long)(p->ainsn.api.insn) + offset),
> > -		   __BUG_INSN_32);
> > +	memcpy(slot, &p->opcode, offset);
> > +	memcpy((void *)((unsigned long)slot + offset), &brk_insn, 4);
> > +	patch_text_nosync(p->ainsn.api.insn, slot, offset + 4);
> >  }
> >  
> >  static void __kprobes arch_prepare_simulate(struct kprobe *p)
> > -- 
> > 2.17.1
> > 
> > 
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-- 
Masami Hiramatsu (Google) <mhiramat@xxxxxxxxxx>