Re: [PATCH v4 12/13] clk: microchip: mpfs: convert periph_clk to clk_gate

[Claudiu.Beznea]

On 30.08.2022 15:52, Conor Dooley wrote:
> With the reset code moved to the recently added reset controller, there
> is no need for custom ops any longer. Remove the custom ops and the
> custom struct by converting to a clk_gate.
> 
> Reviewed-by: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx>
> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>

Reviewed-by: Claudiu Beznea <claudiu.beznea@xxxxxxxxxxxxx>


> ---
>  drivers/clk/microchip/clk-mpfs.c | 72 +++-----------------------------
>  1 file changed, 6 insertions(+), 66 deletions(-)
> 
> diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c
> index 88a200e88e54..fa46176eb9ca 100644
> --- a/drivers/clk/microchip/clk-mpfs.c
> +++ b/drivers/clk/microchip/clk-mpfs.c
> @@ -58,19 +58,11 @@ struct mpfs_cfg_hw_clock {
>  	u32 reg_offset;
>  };
>  
> -struct mpfs_periph_clock {
> -	void __iomem *reg;
> -	u8 shift;
> -};
> -
>  struct mpfs_periph_hw_clock {
> -	struct mpfs_periph_clock periph;
> -	struct clk_hw hw;
> +	struct clk_gate periph;
>  	unsigned int id;
>  };
>  
> -#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw)
> -
>  /*
>   * mpfs_clk_lock prevents anything else from writing to the
>   * mpfs clk block while a software locked register is being written.
> @@ -273,64 +265,12 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *
>   * peripheral clocks - devices connected to axi or ahb buses.
>   */
>  
> -static int mpfs_periph_clk_enable(struct clk_hw *hw)
> -{
> -	struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
> -	struct mpfs_periph_clock *periph = &periph_hw->periph;
> -	u32 reg, val;
> -	unsigned long flags;
> -
> -	spin_lock_irqsave(&mpfs_clk_lock, flags);
> -
> -	reg = readl_relaxed(periph->reg);
> -	val = reg | (1u << periph->shift);
> -	writel_relaxed(val, periph->reg);
> -
> -	spin_unlock_irqrestore(&mpfs_clk_lock, flags);
> -
> -	return 0;
> -}
> -
> -static void mpfs_periph_clk_disable(struct clk_hw *hw)
> -{
> -	struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
> -	struct mpfs_periph_clock *periph = &periph_hw->periph;
> -	u32 reg, val;
> -	unsigned long flags;
> -
> -	spin_lock_irqsave(&mpfs_clk_lock, flags);
> -
> -	reg = readl_relaxed(periph->reg);
> -	val = reg & ~(1u << periph->shift);
> -	writel_relaxed(val, periph->reg);
> -
> -	spin_unlock_irqrestore(&mpfs_clk_lock, flags);
> -}
> -
> -static int mpfs_periph_clk_is_enabled(struct clk_hw *hw)
> -{
> -	struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
> -	struct mpfs_periph_clock *periph = &periph_hw->periph;
> -	u32 reg;
> -
> -	reg = readl_relaxed(periph->reg);
> -	if (reg & (1u << periph->shift))
> -		return 1;
> -
> -	return 0;
> -}
> -
> -static const struct clk_ops mpfs_periph_clk_ops = {
> -	.enable = mpfs_periph_clk_enable,
> -	.disable = mpfs_periph_clk_disable,
> -	.is_enabled = mpfs_periph_clk_is_enabled,
> -};
> -
>  #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) {			\
>  	.id = _id,								\
> -	.periph.shift = _shift,							\
> -	.hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops,		\
> +	.periph.bit_idx = _shift,						\
> +	.periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops,		\
>  				  _flags),					\
> +	.periph.lock = &mpfs_clk_lock,						\
>  }
>  
>  #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].cfg.hw)
> @@ -390,13 +330,13 @@ static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_c
>  		struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i];
>  
>  		periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR;
> -		ret = devm_clk_hw_register(dev, &periph_hw->hw);
> +		ret = devm_clk_hw_register(dev, &periph_hw->periph.hw);
>  		if (ret)
>  			return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
>  					     periph_hw->id);
>  
>  		id = periph_hws[i].id;
> -		data->hw_data.hws[id] = &periph_hw->hw;
> +		data->hw_data.hws[id] = &periph_hw->periph.hw;
>  	}
>  
>  	return 0;