Re: [PATCH v2 3/7] phy: phy-mtk-tphy: add property to set pre-emphasis

[AngeloGioacchino Del Regno]

Il 08/09/22 03:39, Chunfeng Yun ha scritto:
> On Wed, 2022-08-31 at 10:14 +0200, AngeloGioacchino Del Regno wrote:
> > Il 29/08/22 10:08, Chunfeng Yun ha scritto:
> > > Add a property to set usb2 phy's pre-emphasis, it's disabled by
> > > default
> > > on some SoCs.
> > >
> > > Signed-off-by: Chunfeng Yun <chunfeng.yun@xxxxxxxxxxxx>
> > > ---
> > > v2: no changes
> > > ---
> > >    drivers/phy/mediatek/phy-mtk-tphy.c | 10 ++++++++++
> > >    1 file changed, 10 insertions(+)
> > >
> > > diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c
> > > b/drivers/phy/mediatek/phy-mtk-tphy.c
> > > index 8ee7682b8e93..986fde0f63a0 100644
> > > --- a/drivers/phy/mediatek/phy-mtk-tphy.c
> > > +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
> > > @@ -72,6 +72,8 @@
> > >    #define PA5_RG_U2_HS_100U_U3_EN	BIT(11)
> > >    
> > >    #define U3P_USBPHYACR6		0x018
> > > +#define PA6_RG_U2_PRE_EMP		GENMASK(31, 30)
> > > +#define PA6_RG_U2_PRE_EMP_VAL(x)	((0x3 & (x)) << 30)
> >
> > Hello Chunfeng,
> >
> > can you please clarify which SoC is this change referred to?
> These bits are reserved before using 12nm process.
>
> > If I'm not missing anything, there may be a register layout conflict
> As I know these reserved bits are not used before, but now used to tune
> pre-emphasis after supporting 12nm or 5nm process.
>
> > between
> > one version and the other for T-PHYs, for which, it may be a good
> > idea to add
> > a PHY version check before allowing to write settings that are
> > supported only
> > on a specific IP...
> Do you know which SoC used bits, I can confirm it with our DE.

MT8195, MT8186 (and others), RG_USB20_PHY_REV is marked as bit 31:24.

Regards,
Angelo