These CPUs contain the same PMU events (as per the Arm Technical
Reference manuals for Cortex A65 and Neoverse E1)
This de-duplicates event data, and avoids issues in previous E1 event
data (not present in A65 data)
* Missing implementation defined events
* Inclusion of events that are not implemented:
- L1D_CACHE_ALLOCATE
- SAMPLE_POP
- SAMPLE_FEED
- SAMPLE_FILTRATE
- SAMPLE_COLLISION
Signed-off-by: Nick Forrington <nick.forrington@xxxxxxx>