[PATCH v4 2/2] dt-bindings: pci: QCOM Add missing sc7280 aggre0, aggre1 clocks

From: Krishna chaitanya chundru
Date: Thu Sep 08 2022 - 04:47:29 EST


Add missing aggre0 and aggre1 clocks.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx>
---
changes since v3:
- Changed the order of the clocks.
---
Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 22a2aac..54f0785 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -56,11 +56,11 @@ properties:
# Platform constraints are described later.
clocks:
minItems: 3
- maxItems: 12
+ maxItems: 13

clock-names:
minItems: 3
- maxItems: 12
+ maxItems: 13

resets:
minItems: 1
@@ -427,8 +427,8 @@ allOf:
then:
properties:
clocks:
- minItems: 11
- maxItems: 11
+ minItems: 13
+ maxItems: 13
clock-names:
items:
- const: pipe # PIPE clock
@@ -442,6 +442,8 @@ allOf:
- const: slave_q2a # Slave Q2A clock
- const: tbu # PCIe TBU clock
- const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
+ - const: aggre1 # Aggre NoC PCIe1 AXI clock
resets:
maxItems: 1
reset-names:
--
2.7.4