Re: [PATCH] x86/cpu: Avoid writing MSR_IA32_TSX_CTRL when writing it is not supported

From: Andrew Cooper
Date: Thu Sep 08 2022 - 09:35:42 EST

On 07/09/2022 08:32, Hans de Goede wrote:
> Hi,
> On 9/7/22 01:00, Andrew Cooper wrote:
>> On 06/09/2022 22:00, Peter Zijlstra wrote:
>>> On Tue, Sep 06, 2022 at 10:56:47PM +0200, Hans de Goede wrote:
>>>> Hi,
>>>> On 9/6/22 22:43, Peter Zijlstra wrote:
>>>>> On Tue, Sep 06, 2022 at 10:17:43PM +0200, Hans de Goede wrote:
>>>>>> On an Intel Atom N2600 (and presumable other Cedar Trail models)
>>>>>> MSR_IA32_TSX_CTRL can be read, causing saved_msr.valid to be set for it
>>>>>> by msr_build_context().
>>>>>> This causes restore_processor_state() to try and restore it, but writing
>>>>>> this MSR is not allowed on the Intel Atom N2600 leading to:
>>>>> FWIW, virt tends to do this same thing a lot. They'll allow reading
>>>>> random MSRs and only fail on write.
>>>> Right. So I guess I should send a v2 with an updated commit
>>>> message mentioning this ?
>>> Nah, just saying this is a somewhat common pattern with MSRs.
>>> The best ones are the one where writing the value read is invalid :/ or
>>> those who also silently eat a 0 write just for giggles. Luckily that
>>> doesn't happen often.
>> Several comments.  First of all, MSR_TSX_CTRL is a fully read/write
>> MSR.  If virt is doing this wrong, fix the hypervisor.  But this doesn't
>> look virt related?
>> More importantly, MSR_TSX_CTRL does not plausibly exist on an Atom
>> N2600, as it is more than a decade old.
>> MSR_TSX_CTRL was retrofitted in microcode to the MDS_NO, TAA-vulnerable
>> CPUs which is a very narrow range from about 1 quarter of 2019 which
>> includes Cascade Lake, and then included architecturally on subsequent
>> parts which support TSX.
>> pm_save_spec_msr() is totally broken.  It's poking MSRs blindly without
>> checking the enumeration of the capability first.
> Note I did to a different version of this patch before this which did
> add a capability check, but I only send that to various x86-folks +
> x86@xxxxxxxxxx which as Peter pointed out is an alias not a list,
> so you will not have seen that earlier version.
> I have attached the earlier version to this email.

In answer to your question in the patch, no the order doesn't matter,
despite the overlapping interactions between TSX_CTRL and MCU_OPT_CTRL.