RE: BD71847 clk driver disables clk-32k-out causing RTC/WDT failure

[Peng Fan]

> -----Original Message-----
> From: Peng Fan <peng.fan@xxxxxxx>
> Sent: 2022年9月9日 14:57
> To: Marek Vasut <marex@xxxxxxx>; tharvey@xxxxxxxxxxxxx; Stephen
> Boyd <sboyd@xxxxxxxxxx>
> Cc: Matti Vaittinen <mazziesaccount@xxxxxxxxx>; linux-clk <linux-
> clk@xxxxxxxxxxxxxxx>; open list <linux-kernel@xxxxxxxxxxxxxxx>; Fabio
> Estevam <festevam@xxxxxxxxx>; Shawn Guo <shawnguo@xxxxxxxxxx>; dl-
> linux-imx <linux-imx@xxxxxxx>; Michael Turquette
> <mturquette@xxxxxxxxxxxx>
> Subject: RE: BD71847 clk driver disables clk-32k-out causing RTC/WDT failure
> 
> > Subject: Re: BD71847 clk driver disables clk-32k-out causing RTC/WDT
> > failure
> >
> > On 9/9/22 04:06, Peng Fan wrote:
> > >> Subject: Re: BD71847 clk driver disables clk-32k-out causing
> > >> RTC/WDT failure
> > >>
> > >> On 9/8/22 21:25, Tim Harvey wrote:
> > >>> On Thu, Sep 8, 2022 at 9:55 AM Marek Vasut <marex@xxxxxxx>
> wrote:
> > >>>>
> > >>>> On 9/8/22 18:00, Tim Harvey wrote:
> > >>>>> On Thu, Sep 1, 2022 at 9:14 PM Matti Vaittinen
> > >> <mazziesaccount@xxxxxxxxx> wrote:
> > >>>>>>
> > >>>>>> Hi Tim,
> > >>>>>>
> > >>>>>> On 9/2/22 01:23, Tim Harvey wrote:
> > >>>>>>> Greetings,
> > >>>>>>>
> > >>>>>>> I've found that the bd71847 clk driver
> > >> (CONFIG_COMMON_CLK_BD718XX
> > >>>>>>> drivers/clk/clk-bd718x7.c) disables clk-32k-out (the BD71847
> > >>>>>>> C32K_OUT
> > >>>>>>> pin) which is connected IMX8MM RTC_XTALI which ends up
> > disabling
> > >>>>>>> the IMX RTC as well as the IMX WDOG functionality.
> > >>>>>>
> > >>>>>> //snip
> > >>>>>>
> > >>>>>>> This happens via clk_unprepare_unused() as nothing is flagging
> > >>>>>>> the clk-32k-out as being used. What should be added to the
> > >>>>>>> device-tree to signify that this clk is indeed necessary and
> > >>>>>>> should
> > not be disabled?
> > >>>>>>
> > >>>>>> I have seen following proposal from Marek Vasut:
> > >>>>>>
> > >>>>>>
> > >> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fl
> > >>>>>> ore.kernel.org%2Fall%2F20220517235919.200375-1-
> > >> marex%40denx.de%2FT%
> > >>>>>>
> > >>
> >
> 2F%23m52d6d0831bf43d5f293e35cb27f3021f278d0564&amp;data=05%7C0
> > >> 1%7Cp
> > >>>>>>
> > >>
> >
> eng.fan%40nxp.com%7C07d48edcc47c4694e08208da91da2bf4%7C686ea1d
> > >> 3bc2b
> > >>>>>>
> > >>
> > 4c6fa92cd99c5c301635%7C0%7C0%7C637982664162868785%7CUnknown%
> > >> 7CTWFpb
> > >>>>>>
> > >>
> >
> GZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI
> > >> 6
> > >>>>>>
> > >>
> > Mn0%3D%7C3000%7C%7C%7C&amp;sdata=uF26u9g4onuqCWzPRAvD%2F%
> > >> 2FLByaEhh5
> > >>>>>> Dtah9K8CcAOAM%3D&amp;reserved=0
> > >>>>>>
> > >>>>>> I am not sure if the discussion is completed though. I guess it
> > >>>>>> was agreed this was needed/usefull and maybe the remaining
> > >>>>>> thing to decide was just the property naming.
> > >>>>>>
> > >>>>>> Best Regards
> > >>>>>>            -- Matti
> > >>>>>>
> > >>>>>
> > >>>>> Thanks Matti,
> > >>>>>
> > >>>>> Marek - has there been any progress on determining how best to
> > >>>>> keep certain clocks from being disabled?
> > >>>>
> > >>>> No. You can read the discussion above.
> > >>>
> > >>> Marek,
> > >>>
> > >>> I wasn't on the linux-clk list at that time so can't respond to
> > >>> the thread but the discussion seems to have died out a couple of
> > >>> months ago with no agreement between you or Stephen on how to
> deal with it.
> > >>>
> > >>> So where do we take this from here? It looks like there are about
> > >>> 18 boards with dt's using "rohm,bd718*" which would all have non
> > >>> working RTC/WDOG with CONFIG_COMMON_CLK_BD718XX enabled
> > (which it is
> > >>> in
> > >>> arch/arm64/configs/defconfig) right?
> > >
> > > Is there any requirement that the bd718xx clk needs to be runtime
> on/off?
> >
> > Yes, the 32kHz clock on BD71xxx should behave like any other clock,
> > unless specified otherwise, see below.
> >
> > > I suppose the clk should always be never be off, if yes, why not
> > > have
> > something:
> >
> > What is needed in this specific case of BD718xx is I think clock
> > consumer on the MX8M clock driver side which would claim the 32kHz
> > input from the PMIC and up the clock enable count to keep the 32 kHz
> > clock always on. The PMIC is most likely supplying 32 kHz clock to the
> > MX8M, which if the 32 kHz clock are turned off would hang (I observed
> that before too).
> 
> i.MX8M has internal 32 KHz XTAL module, why need external pmic 32KHz
> feed in?

Ignore this comment, it still need external osc.

Regards,
Peng.

> 
> Thanks,
> Peng.
> >
> > What I tried to address in this thread is a generic problem which
> > commonly appears on various embedded systems, except every time
> anyone
> > tried to solve it in a generic manner, it was rejected or they gave up.
> >
> > The problem is this -- you have an arbitrary clock, and you need to
> > keep it running always otherwise the system fails, and you do not have
> > a clock consumer in the DT for whatever reason e.g. because the SoC is
> > only used as a clock source for some unrelated clock net. There must
> > be a way to mark the clock as "never disable these", i.e. critical-clock.
> > (I feel like I keep repeating this over and over in this thread, so
> > please read the whole thread backlog)