Re: [PATCH] spi: meson-spicc: add support for DMA

[Neil Armstrong]

On 14/09/2022 13:19, Arnd Bergmann wrote:
> On Tue, Sep 13, 2022, at 4:03 PM, Neil Armstrong wrote:
>
> > +static void meson_spicc_setup_dma_burst(struct meson_spicc_device *spicc)
> > +{
> ...
> > +	/* Setup burst length */
> > +	writel_relaxed(ld_ctr1, spicc->base + SPICC_LD_CNTL1);
> > +
> > +	writel_relaxed(SPICC_DMA_ENABLE | SPICC_DMA_URGENT |
> > +		       FIELD_PREP(SPICC_TXFIFO_THRESHOLD_MASK, txfifo_thres) |
> > +		       FIELD_PREP(SPICC_READ_BURST_MASK, read_req) |
> > +		       FIELD_PREP(SPICC_RXFIFO_THRESHOLD_MASK, rxfifo_thres) |
> > +		       FIELD_PREP(SPICC_WRITE_BURST_MASK, write_req),
> > +		       spicc->base + SPICC_DMAREG);
> > +}
>
> It looks like this last writel_relaxed() starts the DMA, but I don't
> see any barrier that serializes it against the memory access, which
> could still be in a store buffer.

You're right this one restarts a DMA, so yeah it should not have the relaxed accessor.

But the one starting the first DMA is in another place and aswell should not use relaxed.

> > + /* Sometimes, TC gets triggered while the RX fifo isn't fully flushed *
> > + if (spicc->using_dma) {
> > +          unsigned int rxfifo_count = FIELD_GET(SPICC_RXCNT_MASK,
> > +                       readl_relaxed(spicc->base + SPICC_TESTREG));
>
> Same here in the interrupt controller, I don't see anything enforcing
> the DMA to actually complete before the readl_relaxed().

I don't see the relathionship between a register relaxed read and the DMA not finishing
writing the data in uncached memory, for me it's 2 unrelated things.

> At the very minimum, I think these two have to use non-relaxed
> accessors when adding DMA support, but an easier approach would
> be to use those consistently throughout the driver.

I'll do a check of those accessors for v2.

>       Arnd
Thanks,
Neil