Re: [PATCH 6/8] net: ethernet: ti: am65-cpsw: Add support for SGMII mode for J7200 CPSW5G

[Siddharth Vadapalli]

Hello Russell,

On 14/09/22 21:14, Russell King (Oracle) wrote:
> On Wed, Sep 14, 2022 at 03:20:51PM +0530, Siddharth Vadapalli wrote:
>> Add support for SGMII mode in both fixed-link MAC2MAC master mode and
>> MAC2PHY modes for CPSW5G ports.
>>
>> Add SGMII mode to the list of extra_modes in j7200_cpswxg_pdata.
>>
>> The MAC2PHY mode has been tested in fixed-link mode using a bootstrapped
>> PHY. The MAC2MAC mode has been tested by a customer with J7200 SoC on
>> their device.
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@xxxxxx>
>> ---
>>  drivers/net/ethernet/ti/am65-cpsw-nuss.c | 19 ++++++++++++++++---
>>  1 file changed, 16 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
>> index 1739c389af20..3f40178436ff 100644
>> --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
>> +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
>> @@ -75,7 +75,15 @@
>>  #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2       0x31C
>>  
>>  #define AM65_CPSW_SGMII_CONTROL_REG		0x010
>> +#define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG	0x018
> 
> This doesn't seem to be used in this patch, should it be part of some
> other patch in the series?
> 
>>  #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE	BIT(0)
>> +#define AM65_CPSW_SGMII_CONTROL_MASTER_MODE	BIT(5)
> 
> Ditto.
> 
>> +
>> +#define MAC2MAC_MR_ADV_ABILITY_BASE		(BIT(15) | BIT(0))
>> +#define MAC2MAC_MR_ADV_ABILITY_FULLDUPLEX	BIT(12)
>> +#define MAC2MAC_MR_ADV_ABILITY_1G		BIT(11)
>> +#define MAC2MAC_MR_ADV_ABILITY_100M		BIT(10)
>> +#define MAC2PHY_MR_ADV_ABILITY			BIT(0)
> 
> Most of the above don't seem to be used, and the only one that seems to
> be used is used in a variable declaration where the variable isn't used,
> and thus us also unused.
> 
>>  
>>  #define AM65_CPSW_CTL_VLAN_AWARE		BIT(1)
>>  #define AM65_CPSW_CTL_P0_ENABLE			BIT(2)
>> @@ -1493,6 +1501,7 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in
>>  	struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data,
>>  							  phylink_config);
>>  	struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
>> +	u32 mr_adv_ability = MAC2MAC_MR_ADV_ABILITY_BASE;
> 
> This doesn't seem to be used; should it be part of a different patch?
> 
> I get the impression that most of this patch should be elsewhere in this
> series.

Thank you for pointing it out. These should have been a part of the
previous patch [PATCH 5/8]. Sorry for the confusion. I will fix this in
the v2 series.

Regards,
Siddharth.