Re: [PATCH v2 14/19] dt-bindings: memory: snps: Detach Zynq DDRC controller support

[Rob Herring]

On Sat, 10 Sep 2022 22:42:32 +0300, Serge Semin wrote:
> The Zynq A05 DDRC controller has nothing in common with DW uMCTL2 DDRC:
> the CSRs layout is absolutely different and it doesn't support IRQs unlike
> DW uMCTL2 DDR controller of all versions (v1.x, v2.x and v3.x). Thus there
> is no any reason to have these controllers described in the same bindings.
> Let's split the DT-schema up.
> 
> Note since the synopsys,ddrc-ecc.yaml schema describes the Synopsys DW
> uMCTL2 DDR controller only, we need to accordingly fix the device
> descriptions.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
> 
> ---
> 
> Changelog v2:
> - Move Synopsys DW uMCTL2 DDRC bindings file renaming to a separate
>   patch. (@Krzysztof)
> ---
>  .../memory-controllers/synopsys,ddrc-ecc.yaml | 63 ++++++-------------
>  .../xlnx,zynq-ddrc-a05.yaml                   | 38 +++++++++++
>  MAINTAINERS                                   |  1 +
>  3 files changed, 59 insertions(+), 43 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
> 

Reviewed-by: Rob Herring <robh@xxxxxxxxxx>