Re: linux-next: manual merge of the kvm-arm tree with the arm64 tree

[Marc Zyngier]

Hi Stephen,

Thanks for the heads up.

On Mon, 19 Sep 2022 05:05:31 +0100,
Stephen Rothwell <sfr@xxxxxxxxxxxxxxxx> wrote:
> 
> Hi all,
> 
> Today's linux-next merge of the kvm-arm tree got a conflict in:
> 
>   arch/arm64/kvm/sys_regs.c
> 
> between commit:
> 
>   55adc08d7e64 ("arm64/sysreg: Add _EL1 into ID_AA64PFR0_EL1 definition names")
> 
> from the arm64 tree and commit:
> 
>   cdd5036d048c ("KVM: arm64: Drop raz parameter from read_id_reg()")
> 
> from the kvm-arm tree.
> 
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging.  You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.
> 
> -- 
> Cheers,
> Stephen Rothwell
> 
> diff --cc arch/arm64/kvm/sys_regs.c
> index 2ef1121ab844,9569772cf09a..000000000000
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@@ -1208,9 -1210,9 +1210,9 @@@ static int set_id_aa64pfr0_el1(struct k
>   		return -EINVAL;
>   
>   	/* We can only differ with CSV[23], and anything else is an error */
> - 	val ^= read_id_reg(vcpu, rd, false);
> + 	val ^= read_id_reg(vcpu, rd);
>  -	val &= ~((0xFUL << ID_AA64PFR0_CSV2_SHIFT) |
>  -		 (0xFUL << ID_AA64PFR0_CSV3_SHIFT));
>  +	val &= ~((0xFUL << ID_AA64PFR0_EL1_CSV2_SHIFT) |
>  +		 (0xFUL << ID_AA64PFR0_EL1_CSV3_SHIFT));
>   	if (val)
>   		return -EINVAL;

Catalin, Will: in order to avoid further conflicts, I've taken the
liberty to merge the arm64/for-next/sysreg branch into kvmarm/next.
Let me know if that's a problem.

Also, I've resolved the conflict in a slightly different way. Not that
the above was wrong in any way, but we might as well fix it in a more
idiomatic way:

 	/* We can only differ with CSV[23], and anything else is an error */
 	val ^= read_id_reg(vcpu, rd);
-	val &= ~((0xFUL << ID_AA64PFR0_CSV2_SHIFT) |
-		 (0xFUL << ID_AA64PFR0_CSV3_SHIFT));
+	val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) |
+		 ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3));
 	if (val)
 		return -EINVAL;

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.