[PATCH] clk: renesas: r9a07g043: Hide WDT2 clock and reset entries for RZ/Five

From: Prabhakar
Date: Mon Sep 19 2022 - 08:00:22 EST


From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Make the clock and reset entries for WDT2 only visible for RZ/G2UL (ARM64)
as the RZ/Five SoC doesn't have the WDT2 channel.

While at it, add the WDT2 clocks to r9a07g043_crit_mod_clks[] list as WDT
CH2 is specifically to check the operation of Cortex-M33 CPU on the RZ/G2UL
SoC and we dont want to turn off the clocks of WDT2 if it isn't enabled by
Cortex-A55.

Fixes: 95d48d270305 ("clk: renesas: r9a07g043: Add support for RZ/Five SoC")
Reported-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
drivers/clk/renesas/r9a07g043-cpg.c | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 37475465100d..06692274025d 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -158,10 +158,12 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x548, 0),
DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
0x548, 1),
+#ifdef CONFIG_ARM64
DEF_MOD("wdt2_pclk", R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0,
0x548, 4),
DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK,
0x548, 5),
+#endif
DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1,
0x550, 0),
DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0,
@@ -269,7 +271,9 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
+#ifdef CONFIG_ARM64
DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2),
+#endif
DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
@@ -311,6 +315,8 @@ static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
#ifdef CONFIG_ARM64
MOD_CLK_BASE + R9A07G043_GIC600_GICCLK,
MOD_CLK_BASE + R9A07G043_IA55_CLK,
+ MOD_CLK_BASE + R9A07G043_WDT2_PCLK,
+ MOD_CLK_BASE + R9A07G043_WDT2_CLK,
#endif
#ifdef CONFIG_RISCV
MOD_CLK_BASE + R9A07G043_IAX45_CLK,
--
2.25.1