RE: [PATCH v7 3/7] arm64: dts: imx8mp-evk: Add PCIe support

[Hongxing Zhu]

Hi Tim:
Maybe the internal SYSPLL mode is used on Marcel' Verdin iMX8M Plus board.
This mode is not supported on my previous patch-set yet.
 
Hi Marcel:
I guess that the internal SYSPLL mode is used on your Verdin iMX8M Plus board.
Correct me if I'm wrong.

Up to now, this mode is not supported yet, although I had already one temp
solution that i.MX8MP PCIe works on EVK board when SYSPLL is used as reference
clock(fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;) with some HW
reworks.

About this SYSPLL support method, I still have some confusions and need to 
consult Lucas later.
I can send my local patch-set to Lucas and you buddies, let's figure out one
proper solution to enable the internal SYSPLL mode.

Best Regards
Richard Zhu

> -----Original Message-----
> From: Tim Harvey <tharvey@xxxxxxxxxxxxx>
> Sent: 2022年9月20日 5:34
> To: Marcel Ziswiler <marcel.ziswiler@xxxxxxxxxxx>
> Cc: vkoul@xxxxxxxxxx; richard.leitner@xxxxxxxxx;
> alexander.stein@xxxxxxxxxxxxxxx; robh@xxxxxxxxxx; l.stach@xxxxxxxxxxxxxx;
> shawnguo@xxxxxxxxxx; lorenzo.pieralisi@xxxxxxx; p.zabel@xxxxxxxxxxxxxx;
> Hongxing Zhu <hongxing.zhu@xxxxxxx>; bhelgaas@xxxxxxxxxx;
> marex@xxxxxxx; linux-phy@xxxxxxxxxxxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx;
> kernel@xxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
> linux-kernel@xxxxxxxxxxxxxxx; dl-linux-imx <linux-imx@xxxxxxx>;
> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> Subject: Re: [PATCH v7 3/7] arm64: dts: imx8mp-evk: Add PCIe support
> 
> On Mon, Sep 19, 2022 at 8:22 AM Marcel Ziswiler
> <marcel.ziswiler@xxxxxxxxxxx> wrote:
> >
> > Hi Richard et. al.
> >
> > Thank you very much for the i.MX 8MP PCIe support work.
> >
> > On Fri, 2022-09-02 at 16:58 +0800, Richard Zhu wrote:
> > > Add PCIe support on i.MX8MP EVK board.
> > >
> > > Signed-off-by: Richard Zhu
> > > <hongxing.zhu-3arQi8VN3Tc@xxxxxxxxxxxxxxxx>
> > > Tested-by: Marek Vasut <marex-ynQEQJNshbs@xxxxxxxxxxxxxxxx>
> > > Tested-by: Richard Leitner
> > > <richard.leitner-WcANXNA0UjBBDgjK7y7TUQ@xxxxxxxxxxxxxxxx>
> > > Tested-by: Alexander Stein
> > > <alexander.stein-W3o+9BuWjQaZox4op4iWzw@xxxxxxxxxxxxxxxx>
> > > Reviewed-by: Lucas Stach
> > > <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@xxxxxxxxxxxxxxxx>
> > > ---
> > >  arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 53
> > > ++++++++++++++++++++
> > >  1 file changed, 53 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > index f6b017ab5f53..9f1469db554d 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > @@ -5,6 +5,7 @@
> > >
> > >  /dts-v1/;
> > >
> > > +#include <dt-bindings/phy/phy-imx8-pcie.h>
> > >  #include "imx8mp.dtsi"
> > >
> > >  / {
> > > @@ -33,6 +34,12 @@ memory@40000000 {
> > >                       <0x1 0x00000000 0 0xc0000000>;
> > >         };
> > >
> > > +       pcie0_refclk: pcie0-refclk {
> > > +               compatible = "fixed-clock";
> > > +                       #clock-cells = <0>;
> > > +                       clock-frequency = <100000000>;
> > > +       };
> > > +
> > >         reg_can1_stby: regulator-can1-stby {
> > >                 compatible = "regulator-fixed";
> > >                 regulator-name = "can1-stby"; @@ -55,6 +62,17 @@
> > > reg_can2_stby: regulator-can2-stby {
> > >                 enable-active-high;
> > >         };
> > >
> > > +       reg_pcie0: regulator-pcie {
> > > +               compatible = "regulator-fixed";
> > > +               pinctrl-names = "default";
> > > +               pinctrl-0 = <&pinctrl_pcie0_reg>;
> > > +               regulator-name = "MPCIE_3V3";
> > > +               regulator-min-microvolt = <3300000>;
> > > +               regulator-max-microvolt = <3300000>;
> > > +               gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
> > > +               enable-active-high;
> > > +       };
> > > +
> > >         reg_usdhc2_vmmc: regulator-usdhc2 {
> > >                 compatible = "regulator-fixed";
> > >                 pinctrl-names = "default"; @@ -350,6 +368,28 @@
> > > &i2c5 {
> > >          */
> > >  };
> > >
> > > +&pcie_phy {
> > > +       fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
> >
> > While this indeed works on the EVK so far I failed to get this to work
> > on our Verdin iMX8M Plus which requires the fsl,refclk-pad-mode to be
> > IMX8_PCIE_REFCLK_PAD_OUTPUT. It is not quite clear to me what kind of
> clocks I would need specifying in that case.
> >
> > Has anybody by any chance tried on any such HW design?
> >
> > For reference [1] on the Verdin iMX8M Mini the same works very well but the
> clocking seems rather different.
> >
> 
> Marcel,
> 
> Do you have all the patches in Richard's series applied [1]? They got picked up
> in different trees so make sure you have them all. I just tested this series on top
> of 6.0-rc6 with imx8mp-venice-gw74xx and it works fine. This board however
> does have IMX8_PCIE_REFCLK_PAD_INPUT.
> 
> Do you by chance have CLKREQ not hooked up? If so make sure you add a
> 'fsl,clkreq-unsupported' probe to pcie_phy.
> 
> Best Regards,
> 
> Tim
> [1]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchw
> ork.kernel.org%2Fproject%2Flinux-pci%2Flist%2F%3Fseries%3D673548%26sta
> te%3D*&amp;data=05%7C01%7Chongxing.zhu%40nxp.com%7C4a85a32c821
> 34a1992bb08da9a86c054%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7
> C0%7C637992200786521249%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4
> wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7
> C%7C%7C&amp;sdata=I9ZuBCSdyQirGqiJVayRZnz7ypb%2FCCtBUsoLWo6wgdI
> %3D&amp;reserved=0