RE: [PATCH v2 1/1] iommu/vt-d: Avoid unnecessary global IRTE cache invalidation

[Tian, Kevin]

> From: Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx>
> Sent: Wednesday, September 21, 2022 2:58 PM
> 
> Some VT-d hardware implementations invalidate all interrupt remapping
> hardware translation caches as part of SIRTP flow. The VT-d spec adds
> a ESIRTPS (Enhanced Set Interrupt Remap Table Pointer Support, section
> 11.4.2 in VT-d spec) capability bit to indicate this.
> 
> The spec also states in 11.4.4 that hardware also performs global
> invalidation on all interrupt remapping caches as part of Interrupt
> Remapping Disable operation if ESIRTPS capability bit is set.
> 
> This checks the ESIRTPS capability bit and skip software global cache
> invalidation if it's set.
> 
> Signed-off-by: Jacob Pan <jacob.jun.pan@xxxxxxxxxxxxxxx>
> Signed-off-by: Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx>
> Reviewed-by: Jerry Snitselaar <jsnitsel@xxxxxxxxxx>

Reviewed-by: Kevin Tian <kevin.tian@xxxxxxxxx>