Re: [PATCH v2 1/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt

[Palmer Dabbelt]

On Thu, 15 Sep 2022 19:24:55 PDT (-0700), apatel@xxxxxxxxxxxxxxxx wrote:
> Hi Palmer,
>
> On Tue, Aug 30, 2022 at 10:17 AM Anup Patel <apatel@xxxxxxxxxxxxxxxx> wrote:
> > Currently, all flavors of ioremap_xyz() function maps to the generic
> > ioremap() which means any ioremap_xyz() call will always map the
> > target memory as IO using _PAGE_IOREMAP page attributes. This breaks
> > ioremap_cache() and ioremap_wc() on systems with Svpbmt because memory
> > remapped using ioremap_cache() and ioremap_wc() will use _PAGE_IOREMAP
> > page attributes.
> >
> > To address above (just like other architectures), we implement RISC-V
> > specific ioremap_cache() and ioremap_wc() which maps memory using page
> > attributes as defined by the Svpbmt specification.
> >
> > Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
> > Co-developed-by: Mayuresh Chitale <mchitale@xxxxxxxxxxxxxxxx>
> > Signed-off-by: Mayuresh Chitale <mchitale@xxxxxxxxxxxxxxxx>
> > Signed-off-by: Anup Patel <apatel@xxxxxxxxxxxxxxxx>
>
> This is a crucial RC fix. Can you please take this ?

Sorry I missed this, I thought it was just part of the rest of this 
patch set.  That said, I'm not actually sure this is a critical fix: 
sure it's a performance problem, and if some driver is expecting 
ioremap_cache() to go fast then possibly a pretty big one, but the only 
Svpmbt hardware that exists is the D1 and that was just supported this 
release so it's not a regression.  Maybe that's a bit pedantic, but all 
this travel has kind of made things a mess and I'm trying to make sure 
nothing goes off the rails.

Probably a pointless distinction as it'll just get backported anyway, 
but I'm going to hold off on this for now -- it generally looks OK, but 
I don't get back until this weekend and I'm super tired so I'm trying to 
avoid screwing anything up.

> Regards,
> Anup
>
> > ---
> >  arch/riscv/include/asm/io.h      | 10 ++++++++++
> >  arch/riscv/include/asm/pgtable.h |  2 ++
> >  2 files changed, 12 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
> > index 69605a474270..07ac63999575 100644
> > --- a/arch/riscv/include/asm/io.h
> > +++ b/arch/riscv/include/asm/io.h
> > @@ -133,6 +133,16 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
> >  #define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count)
> >  #endif
> >
> > +#ifdef CONFIG_MMU
> > +#define ioremap_wc(addr, size)         \
> > +       ioremap_prot((addr), (size), _PAGE_IOREMAP_WC)
> > +#endif
> > +
> >  #include <asm-generic/io.h>
> >
> > +#ifdef CONFIG_MMU
> > +#define ioremap_cache(addr, size)      \
> > +       ioremap_prot((addr), (size), _PAGE_KERNEL)
> > +#endif
> > +
> >  #endif /* _ASM_RISCV_IO_H */
> > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> > index 7ec936910a96..346b7c1a3eeb 100644
> > --- a/arch/riscv/include/asm/pgtable.h
> > +++ b/arch/riscv/include/asm/pgtable.h
> > @@ -182,6 +182,8 @@ extern struct pt_alloc_ops pt_ops __initdata;
> >  #define PAGE_TABLE             __pgprot(_PAGE_TABLE)
> >
> >  #define _PAGE_IOREMAP  ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO)
> > +#define _PAGE_IOREMAP_WC       ((_PAGE_KERNEL & ~_PAGE_MTMASK) | \
> > +                                _PAGE_NOCACHE)
> >  #define PAGE_KERNEL_IO         __pgprot(_PAGE_IOREMAP)
> >
> >  extern pgd_t swapper_pg_dir[];
> > --
> > 2.34.1