Re: [PATCH v3] PCI: Sanitise firmware BAR assignments behind a PCI-PCI bridge

From: Maciej W. Rozycki
Date: Thu Sep 22 2022 - 20:39:01 EST


On Wed, 21 Sep 2022, Bjorn Helgaas wrote:

> > I have trimmed the change description down as you requested and left the
> > change proper unmodified, as discussed in my earlier response.
>
> I think this is great. It shouldn't have taken me this long, so
> thanks for persevering.

No worries, owing to various distractions it took me way too long to
iterate over this change too.

> I think we can use pci_upstream_bridge() as below. Let me know if
> not.

Based on how the helper has been documented I think you are right. Also
I have verified your branch with my hardware and it still works.

> Here it is as I applied to pci/resource for v6.1:

Thank you! I find your rewritten change description a pleasure to read.

I guess at this stage we'll never find out what the exact configuration
was that has lead to commit 351fc6d1a517 ("PCI: Fix starting basis for
resource requests"). At least it does not stand in the way.

What a mess it was with the firmware side of the earlier PCI systems even
once they've sorted the teething problems of the hardware side! I still
need to figure out how to get PCI interrupt routing to automagically work
in the I/O APIC mode with this x86 machine and its broken MP-table which
reports PCI interrupts as ISA interrupts, and then INTA only (at least our
PIRQ router code now handles PCI-to-PCI bridges in the PIC mode). And it
would have been so easy to get it right even with a fixed table (the BIOS
seems to build the table dynamically for no good reason even though the
wiring is fixed in hardware)!

Maciej