[PATCH v4 0/2] riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores

From: Heiko Stuebner
Date: Tue Oct 04 2022 - 16:37:55 EST

The PMU on T-Head C9xx cores is quite similar to the SSCOFPMF extension
but not completely identical, so this series

changes in v4:
- add new patch to cache sbi mvendor, march and mimp-ids (Atish)
- errata dependencies in one line (Conor)
- make driver detection conditional on CONFIG_ERRATA_THEAD_PMU too (Atish)

changes in v3:
- improve commit message (Atish, Conor)
- IS_ENABLED and BIT() in errata probe (Conor)

The change depends on my cpufeature/t-head errata probe cleanup series [1].

changes in v2:
- use alternatives for the CSR access
- make the irq num selection a bit nicer

There is of course a matching opensbi-part whose most recent implementation
can be found on [0].

[0] https://patchwork.ozlabs.org/project/opensbi/cover/20221004164227.1381825-1-heiko@xxxxxxxxx
[1] https://lore.kernel.org/all/20220905111027.2463297-1-heiko@xxxxxxxxx/

Heiko Stuebner (2):
RISC-V: Cache SBI vendor values
drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head
C9xx cores

arch/riscv/Kconfig.erratas | 13 +++++++++++
arch/riscv/errata/thead/errata.c | 18 +++++++++++++++
arch/riscv/include/asm/errata_list.h | 16 +++++++++++++-
arch/riscv/kernel/sbi.c | 21 +++++++++++++++---
drivers/perf/riscv_pmu_sbi.c | 33 +++++++++++++++++++---------
5 files changed, 87 insertions(+), 14 deletions(-)