Re: [PATCH 2/2] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores
From: Andrew Jones
Date: Wed Oct 05 2022 - 13:39:07 EST
On Tue, Oct 04, 2022 at 10:37:24PM +0200, Heiko Stuebner wrote:
> With the T-HEAD C9XX cores being designed before or during the ratification
> to the SSCOFPMF extension, it implements functionality very similar but
> not equal to it.
> It implements overflow handling and also some privilege-mode filtering.
> While SSCOFPMF supports this for all modes, the C9XX only implements the
> filtering for M-mode and S-mode but not user-mode.
> So add some adaptions to allow the C9XX to still handle
> its PMU through the regular SBI PMU interface instead of defining new
> interfaces or drivers.
> To work properly, this requires a matching change in SBI, though the actual
> interface between kernel and SBI does not change.
> The main differences are a the overflow CSR and irq number.
> As the reading of the overflow-csr is in the hot-path during irq handling,
> use an errata and alternatives to not introduce new conditionals there.
> Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx>
> arch/riscv/Kconfig.erratas | 13 +++++++++++
> arch/riscv/errata/thead/errata.c | 18 +++++++++++++++
> arch/riscv/include/asm/errata_list.h | 16 +++++++++++++-
> drivers/perf/riscv_pmu_sbi.c | 33 +++++++++++++++++++---------
> 4 files changed, 69 insertions(+), 11 deletions(-)
Reviewed-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx>