[GIT PULL] RISC-V Patches for the 6.1 Merge Window, Part 1

[Palmer Dabbelt]

The following changes since commit 568035b01cfb107af8d2e4bd2fb9aea22cf5b868:

  Linux 6.0-rc1 (2022-08-14 15:50:18 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.1-mw1

for you to fetch changes up to 87f81e66e2e84c7e6056413703d732a99c20c09b:

  riscv: enable THP_SWAP for RV64 (2022-10-06 20:03:48 -0700)

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RISC-V Patches for the 6.1 Merge Window, Part 1

* Improvements to the CPU topology subsystem, which fix some issues
  where RISC-V would report bad topology information.
* The default NR_CPUS has increased to XLEN, and the maximum
  configurable value is 512.
* The CD-ROM filesystems have been enabled in the defconfig.
* Support for THP_SWAP has been added for rv64 systems.

There are also a handful of cleanups and fixes throughout the tree.

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I will almost certainly have a part 2 for next week, but I'm not sure how big
it will be: between the conferences and COVID things have been a mess on my
end, that's clearly made this first week pretty small but it's also meant a lot
of stuff on the lists still needs work.  There's also some stuff that's pending
on conflicts, though, so I figured it'd be best to just send this today to make
handling those easier.

I'm still seeing some of these KASAN/pcpu_alloc related panics, but it doesn't
seem like they're more common with these than they are on 6.0 so I think it's
OK to just call these safe.  Aside from that things seem fine with this merged
into master from this morning.

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Anup Patel (2):
      cpuidle: riscv-sbi: Fix CPU_PM_CPU_IDLE_ENTER_xyz() macro usage
      RISC-V: Increase range and default value of NR_CPUS

Conor Dooley (2):
      arm64: topology: move store_cpu_topology() to shared code
      riscv: topology: fix default topology reporting

Heinrich Schuchardt (1):
      riscv: enable CD-ROM file systems in defconfig

Jisheng Zhang (2):
      riscv: compat: s/failed/unsupported if compat mode isn't supported
      riscv: enable THP_SWAP for RV64

Palmer Dabbelt (2):
      Merge tag 'riscv-topo-on-6.0-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ into for-next
      RISC-V: Print SSTC in canonical order

Sergey Matyukevich (2):
      perf: RISC-V: exclude invalid pmu counters from SBI calls
      perf: RISC-V: throttle perf events

 arch/arm64/kernel/topology.c        | 40 -------------------------------------
 arch/riscv/Kconfig                  | 12 +++++++----
 arch/riscv/configs/defconfig        |  3 +++
 arch/riscv/kernel/cpu.c             |  2 +-
 arch/riscv/kernel/process.c         |  2 +-
 arch/riscv/kernel/smpboot.c         |  3 ++-
 drivers/base/arch_topology.c        | 19 ++++++++++++++++++
 drivers/cpuidle/cpuidle-riscv-sbi.c |  7 ++++++-
 drivers/perf/riscv_pmu_legacy.c     |  4 ++--
 drivers/perf/riscv_pmu_sbi.c        | 31 ++++++++++++++++++----------
 include/linux/perf/riscv_pmu.h      |  2 +-
 11 files changed, 63 insertions(+), 62 deletions(-)