Re: [PATCH v2] dt-bindings: net: marvell,pp2: convert to json-schema
From: Marcin Wojtas
Date: Mon Oct 10 2022 - 20:38:43 EST
Hi Michał,
Additional comments inline.
wt., 27 wrz 2022 o 01:22 Michał Grzelak <mig@xxxxxxxxxxxx> napisał(a):
>
> This converts the marvell,pp2 bindings from text to proper schema.
>
> Move 'marvell,system-controller' and 'dma-coherent' properties from
> port up to the controller node, to match what is actually done in DT.
>
> Signed-off-by: Michał Grzelak <mig@xxxxxxxxxxxx>
> ---
> .../devicetree/bindings/net/marvell,pp2.yaml | 241 ++++++++++++++++++
> .../devicetree/bindings/net/marvell-pp2.txt | 141 ----------
> MAINTAINERS | 2 +-
> 3 files changed, 242 insertions(+), 142 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/net/marvell,pp2.yaml
> delete mode 100644 Documentation/devicetree/bindings/net/marvell-pp2.txt
>
> diff --git a/Documentation/devicetree/bindings/net/marvell,pp2.yaml b/Documentation/devicetree/bindings/net/marvell,pp2.yaml
> new file mode 100644
> index 000000000000..6faa4c87dfc6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/marvell,pp2.yaml
> @@ -0,0 +1,241 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/marvell,pp2.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Marvell CN913X / Marvell Armada 375, 7K, 8K Ethernet Controller
> +
> +maintainers:
> + - Marcin Wojtas <mw@xxxxxxxxxxxx>
> + - Russell King <linux@xxxxxxxxxxxx>
> +
> +description: |
> + Marvell Armada 375 Ethernet Controller (PPv2.1)
> + Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
> + Marvell CN913X Ethernet Controller (PPv2.3)
> +
> +properties:
> + compatible:
> + enum:
> + - marvell,armada-375-pp2
> + - marvell,armada-7k-pp22
> +
> + reg:
> + minItems: 3
> + maxItems: 4
> + description: |
> + For "marvell,armada-375-pp2", must contain the following register sets:
> + - common controller registers
> + - LMS registers
> + - one register area per Ethernet port
> + For "marvell,armada-7k-pp22" used by 7K/8K and CN913X, must contain the following register sets:
> + - packet processor registers
> + - networking interfaces registers
> + - CM3 address space used for TX Flow Control
> +
> + clocks:
> + minItems: 2
> + items:
> + - description: main controller clock
> + - description: GOP clock
> + - description: MG clock
> + - description: MG Core clock
> + - description: AXI clock
> +
> + clock-names:
> + minItems: 2
> + items:
> + - const: pp_clk
> + - const: gop_clk
> + - const: mg_clk
> + - const: mg_core_clk
> + - const: axi_clk
> +
> + dma-coherent: true
> + '#size-cells': true
> + '#address-cells': true
> +
> + marvell,system-controller:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: a phandle to the system controller.
> +
> +patternProperties:
> + '^eth[0-9a-f]*(@.*)?$':
> + type: object
> + properties:
> + interrupts:
> + minItems: 1
> + maxItems: 10
> + description: interrupt(s) for the port
> +
> + interrupt-names:
> + items:
> + - const: hif0
> + - const: hif1
> + - const: hif2
> + - const: hif3
> + - const: hif4
> + - const: hif5
> + - const: hif6
> + - const: hif7
> + - const: hif8
> + - const: link
> +
> + description: >
> + if more than a single interrupt for is given, must be the
> + name associated to the interrupts listed. Valid names are:
> + "hifX", with X in [0..8], and "link". The names "tx-cpu0",
> + "tx-cpu1", "tx-cpu2", "tx-cpu3" and "rx-shared" are supported
> + for backward compatibility but shouldn't be used for new
> + additions.
> +
> + port-id:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: ID of the port from the MAC point of view.
> +
> + phy:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: >
> + a phandle to a phy node defining the PHY address
> + (as the reg property, a single integer).
> +
> + phy-mode:
> + $ref: "ethernet-controller.yaml#/properties/phy-mode"
> +
> + marvell,loopback:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description: port is loopback mode.
> +
> + gop-port-id:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: >
> + only for marvell,armada-7k-pp22, ID of the port from the
> + GOP (Group Of Ports) point of view. This ID is used to index the
> + per-port registers in the second register area.
> +
> + required:
> + - interrupts
> + - port-id
> + - phy-mode
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +allOf:
> + - $ref: ethernet-controller.yaml#
> + - if:
> + properties:
> + compatible:
> + const: marvell,armada-7k-pp22
> + then:
> + patternProperties:
> + '^eth[0-9a-f]*(@.*)?$':
> + required:
> + - gop-port-id
For this variant, 'marvell,system-controller' should also be marked as required.
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + // For Armada 375 variant
> + #include <dt-bindings/interrupt-controller/mvebu-icu.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + ethernet@f0000 {
> + compatible = "marvell,armada-375-pp2";
> + reg = <0xf0000 0xa000>,
> + <0xc0000 0x3060>,
> + <0xc4000 0x100>,
> + <0xc5000 0x100>;
> + clocks = <&gateclk 3>, <&gateclk 19>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "pp_clk", "gop_clk";
> +
> + eth0: eth0@c4000 {
> + reg = <0xc4000>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + port-id = <0>;
> + phy = <&phy0>;
> + phy-mode = "gmii";
> + };
> +
> + eth1: eth1@c5000 {
> + reg = <0xc5000>;
> + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> + port-id = <1>;
> + phy = <&phy3>;
> + phy-mode = "gmii";
> + };
> + };
> +
> + - |
> + // For Armada 7k/8k and Cn913x variants
> + #include <dt-bindings/interrupt-controller/mvebu-icu.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + cpm_ethernet: ethernet@0 {
> + compatible = "marvell,armada-7k-pp22";
> + reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
> + clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,
> + <&cpm_syscon0 1 5>, <&cpm_syscon0 1 6>, <&cpm_syscon0 1 18>;
s/syscon0/clk/
Also add missing marvell,system-controller.
Best regards,
Marcin