Re: [PATCH 1/2] i2c: npcm7xx: Group bank 0/1 registers together for readability

[Tali Perry]

Reviewed-by: Tali Perry <tali.perry1@xxxxxxxxx>

Thanks Jonathan!

On Sat, Oct 8, 2022 at 3:59 PM Jonathan Neuschäfer
<j.neuschaefer@xxxxxxx> wrote:
>
> The unlabelled registers NPCM_I2CCTL4 to NPCM_I2CSCLHT overlap with the
> bank 1 registers below, and they are accessed after selecting bank 0, so
> they clearly belong to bank 0.
>
> Move them together with the other bank 0 registers, and move the
> unrelated definition of npcm_i2caddr down to keep the banked registers
> in one piece.
>
> Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@xxxxxxx>
> ---
>  drivers/i2c/busses/i2c-npcm7xx.c | 31 +++++++++++++++----------------
>  1 file changed, 15 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm7xx.c
> index 0c365b57d9572..9a7a2d0bf5765 100644
> --- a/drivers/i2c/busses/i2c-npcm7xx.c
> +++ b/drivers/i2c/busses/i2c-npcm7xx.c
> @@ -106,7 +106,7 @@ enum i2c_addr {
>  #define NPCM_I2CCST3                   0x19
>  #define I2C_VER                                0x1F
>
> -/*BANK0 regs*/
> +/* BANK 0 regs */
>  #define NPCM_I2CADDR3                  0x10
>  #define NPCM_I2CADDR7                  0x11
>  #define NPCM_I2CADDR4                  0x12
> @@ -115,6 +115,20 @@ enum i2c_addr {
>  #define NPCM_I2CADDR9                  0x15
>  #define NPCM_I2CADDR6                  0x16
>  #define NPCM_I2CADDR10                 0x17
> +#define NPCM_I2CCTL4                   0x1A
> +#define NPCM_I2CCTL5                   0x1B
> +#define NPCM_I2CSCLLT                  0x1C /* SCL Low Time */
> +#define NPCM_I2CFIF_CTL                        0x1D /* FIFO Control */
> +#define NPCM_I2CSCLHT                  0x1E /* SCL High Time */
> +
> +/* BANK 1 regs */
> +#define NPCM_I2CFIF_CTS                        0x10 /* Both FIFOs Control and Status */
> +#define NPCM_I2CTXF_CTL                        0x12 /* Tx-FIFO Control */
> +#define NPCM_I2CT_OUT                  0x14 /* Bus T.O. */
> +#define NPCM_I2CPEC                    0x16 /* PEC Data */
> +#define NPCM_I2CTXF_STS                        0x1A /* Tx-FIFO Status */
> +#define NPCM_I2CRXF_STS                        0x1C /* Rx-FIFO Status */
> +#define NPCM_I2CRXF_CTL                        0x1E /* Rx-FIFO Control */
>
>  #if IS_ENABLED(CONFIG_I2C_SLAVE)
>  /*
> @@ -131,21 +145,6 @@ static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = {
>  };
>  #endif
>
> -#define NPCM_I2CCTL4                   0x1A
> -#define NPCM_I2CCTL5                   0x1B
> -#define NPCM_I2CSCLLT                  0x1C /* SCL Low Time */
> -#define NPCM_I2CFIF_CTL                        0x1D /* FIFO Control */
> -#define NPCM_I2CSCLHT                  0x1E /* SCL High Time */
> -
> -/* BANK 1 regs */
> -#define NPCM_I2CFIF_CTS                        0x10 /* Both FIFOs Control and Status */
> -#define NPCM_I2CTXF_CTL                        0x12 /* Tx-FIFO Control */
> -#define NPCM_I2CT_OUT                  0x14 /* Bus T.O. */
> -#define NPCM_I2CPEC                    0x16 /* PEC Data */
> -#define NPCM_I2CTXF_STS                        0x1A /* Tx-FIFO Status */
> -#define NPCM_I2CRXF_STS                        0x1C /* Rx-FIFO Status */
> -#define NPCM_I2CRXF_CTL                        0x1E /* Rx-FIFO Control */
> -
>  /* NPCM_I2CST reg fields */
>  #define NPCM_I2CST_XMIT                        BIT(0)
>  #define NPCM_I2CST_MASTER              BIT(1)
> --
> 2.35.1
>