[PATCH 1/3] dt-bindings: PCI: cdns: Add PHY latency properties

[Dominic Rath]

From: Alexander Bahle <bahle@xxxxxxxxxxxxxxx>

Add "cdns,tx-phy-latency-ps" and "cdns,rx-phy-latency-ps" DT bindings for
setting the PCIe PHY latencies.
The properties expect a list of uint32 PHY latencies in picoseconds for
every supported speed starting at PCIe Gen1, e.g.:

  max-link-speed = <2>;
  tx-phy-latency-ps = <100000 200000>; /* Gen1: 100ns, Gen2: 200ns */
  rx-phy-latency-ps = <150000 250000>; /* Gen1: 150ns, Gen2: 250ns */

There should be a value for every supported speed.

Signed-off-by: Alexander Bahle <bahle@xxxxxxxxxxxxxxx>
Signed-off-by: Dominic Rath <rath@xxxxxxxxxxxxxxx>
---
 .../bindings/pci/cdns,cdns-pcie-ep.yaml       |  2 ++
 .../bindings/pci/cdns,cdns-pcie-host.yaml     |  2 ++
 .../devicetree/bindings/pci/cdns-pcie-ep.yaml | 20 +++++++++++++++++++
 .../bindings/pci/cdns-pcie-host.yaml          | 20 +++++++++++++++++++
 4 files changed, 44 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
index e6ef1012a580..ce239da3a592 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
@@ -45,6 +45,8 @@ examples:
                 max-functions = /bits/ 8 <8>;
                 phys = <&pcie_phy0>;
                 phy-names = "pcie-phy";
+                cdns,tx-phy-latency-ps = <138800 69400>;
+                cdns,rx-phy-latency-ps = <185200 92600>;
         };
     };
 ...
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
index 293b8ec318bc..a7f4e3909c51 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
@@ -70,6 +70,8 @@ examples:
 
             phys = <&pcie_phy0>;
             phy-names = "pcie-phy";
+            cdns,tx-phy-latency-ps = <138800 69400>;
+            cdns,rx-phy-latency-ps = <185200 92600>;
         };
     };
 ...
diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml
index baeafda36ebe..95ea273372d1 100644
--- a/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml
@@ -21,4 +21,24 @@ properties:
     maximum: 32
     default: 32
 
+  cdns,tx-phy-latency-ps:
+    description:
+      The PHY latencies for the TX direction applied to the PTM timestamps. Most
+      PCIe PHYs have asynchronous latencies for their RX and TX paths. To obtain
+      accurate PTM timestamps, the PCIe PTM specification requires that the time
+      at which the first serial bit is present on the serial lines be taken.
+      Should contain picosecond latency values for each supported speed,
+      starting with Gen1 latency.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+
+  cdns,rx-phy-latency-ps:
+    description:
+      The PHY latencies for the RX direction applied to the PTM timestamps. Most
+      PCIe PHYs have asynchronous latencies for their RX and TX paths. To obtain
+      accurate PTM timestamps, the PCIe PTM specification requires that the time
+      at which the first serial bit is present on the serial lines be taken.
+      Should contain picosecond latency values for each supported speed,
+      starting with Gen1 latency.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+
 additionalProperties: true
diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml
index a944f9bfffff..66f5a6449e1e 100644
--- a/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml
@@ -32,6 +32,26 @@ properties:
     default: 32
     deprecated: true
 
+  cdns,tx-phy-latency-ps:
+    description:
+      The PHY latencies for the TX direction applied to the PTM timestamps. Most
+      PCIe PHYs have asynchronous latencies for their RX and TX paths. To obtain
+      accurate PTM timestamps, the PCIe PTM specification requires that the time
+      at which the first serial bit is present on the serial lines be taken.
+      Should contain picosecond latency values for each supported speed,
+      starting with Gen1 latency.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+
+  cdns,rx-phy-latency-ps:
+    description:
+      The PHY latencies for the RX direction applied to the PTM timestamps. Most
+      PCIe PHYs have asynchronous latencies for their RX and TX paths. To obtain
+      accurate PTM timestamps, the PCIe PTM specification requires that the time
+      at which the first serial bit is present on the serial lines be taken.
+      Should contain picosecond latency values for each supported speed,
+      starting with Gen1 latency.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+
   msi-parent: true
 
 additionalProperties: true
-- 
2.36.0