[PATCH v1 1/3] dt-bindings: PCI: mediatek-gen3: Add iommu and power-domain support

[Tinghan Shen]

From: Jianjun Wang <jianjun.wang@xxxxxxxxxxxx>

Add iommu and power-domain support, and add examples for MT8195, which
has two PCIe ports with different clocks and phys.

Signed-off-by: Jianjun Wang <jianjun.wang@xxxxxxxxxxxx>
Signed-off-by: TingHan Shen <tinghan.shen@xxxxxxxxxxxx>
---
 .../bindings/pci/mediatek-pcie-gen3.yaml      | 115 ++++++++++++++++++
 1 file changed, 115 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
index c00be39af64e..089074b5fa95 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -70,6 +70,12 @@ properties:
     minItems: 1
     maxItems: 8
 
+  iommu-map:
+    maxItems: 1
+
+  iommu-map-mask:
+    maxItems: 1
+
   resets:
     minItems: 1
     maxItems: 2
@@ -107,6 +113,9 @@ properties:
     items:
       - const: pcie-phy
 
+  power-domains:
+    maxItems: 1
+
   '#interrupt-cells':
     const: 1
 
@@ -191,3 +200,109 @@ examples:
             };
         };
     };
+
+  - |
+    #include <dt-bindings/clock/mt8195-clk.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/memory/mt8195-memory-port.h>
+    #include <dt-bindings/phy/phy.h>
+    #include <dt-bindings/power/mt8195-power.h>
+
+    bus {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        pcie0: pcie@112f0000 {
+            compatible = "mediatek,mt8195-pcie", "mediatek,mt8192-pcie";
+            device_type = "pci";
+            #address-cells = <3>;
+            #size-cells = <2>;
+            reg = <0x00 0x112f0000 0x00 0x4000>;
+            reg-names = "pcie-mac";
+            interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
+            bus-range = <0x00 0xff>;
+            ranges = <0x81000000 0x00 0x20000000 0x00
+                      0x20000000 0x00 0x200000>,
+                     <0x82000000 0x00 0x20200000 0x00
+                      0x20200000 0x00 0x3e00000>;
+
+            iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
+            iommu-map-mask = <0x0>;
+
+            clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
+                     <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
+                     <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
+                     <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
+                     <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
+                     <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
+            clock-names = "pl_250m", "tl_26m", "tl_96m",
+                          "tl_32k", "peri_26m", "peri_mem";
+            assigned-clocks = <&topckgen CLK_TOP_TL>;
+            assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
+
+            phys = <&pciephy>;
+            phy-names = "pcie-phy";
+
+            power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
+
+            #interrupt-cells = <1>;
+            interrupt-map-mask = <0 0 0 0x7>;
+            interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+                            <0 0 0 2 &pcie_intc0 1>,
+                            <0 0 0 3 &pcie_intc0 2>,
+                            <0 0 0 4 &pcie_intc0 3>;
+            pcie_intc0: interrupt-controller {
+                      #address-cells = <0>;
+                      #interrupt-cells = <1>;
+                      interrupt-controller;
+            };
+        };
+
+        pcie1: pcie@112f8000 {
+            compatible = "mediatek,mt8195-pcie", "mediatek,mt8192-pcie";
+            device_type = "pci";
+            #address-cells = <3>;
+            #size-cells = <2>;
+            reg = <0x00 0x112f8000 0x00 0x4000>;
+            reg-names = "pcie-mac";
+            interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
+            bus-range = <0x00 0xff>;
+            ranges = <0x81000000 0x00 0x24000000 0x00
+                      0x24000000 0x00 0x200000>,
+                     <0x82000000 0x00 0x24200000 0x00
+                      0x24200000 0x00 0x3e00000>;
+
+            iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
+            iommu-map-mask = <0x0>;
+
+            clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
+                     <&clk26m>,
+                     <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
+                     <&clk26m>,
+                     <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
+                     /* Designer has connect pcie1 with peri_mem_p0 clock */
+                     <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
+            clock-names = "pl_250m", "tl_26m", "tl_96m",
+                          "tl_32k", "peri_26m", "peri_mem";
+            assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
+            assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
+
+            phys = <&u3port1 PHY_TYPE_PCIE>;
+            phy-names = "pcie-phy";
+
+            power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
+
+            #interrupt-cells = <1>;
+            interrupt-map-mask = <0 0 0 0x7>;
+            interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+                            <0 0 0 2 &pcie_intc1 1>,
+                            <0 0 0 3 &pcie_intc1 2>,
+                            <0 0 0 4 &pcie_intc1 3>;
+            pcie_intc1: interrupt-controller {
+                      #address-cells = <0>;
+                      #interrupt-cells = <1>;
+                      interrupt-controller;
+            };
+        };
+    };
-- 
2.18.0