Add pcie and pcie phy nodes for mt8195.
Signed-off-by: Jianjun Wang <jianjun.wang@xxxxxxxxxxxx>
Signed-off-by: Tinghan Shen <tinghan.shen@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 143 +++++++++++++++++++++++
1 file changed, 143 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index d03f0c2b8233..903e92d6156f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1182,6 +1182,104 @@
status = "disabled";
};
+ pcie0: pcie@112f0000 {
+ compatible = "mediatek,mt8195-pcie",
+ "mediatek,mt8192-pcie";
+
+ phys = <&pciephy>;
+ phy-names = "pcie-phy";
+
+ power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ };
+
+ pcie1: pcie@112f8000 {
+ compatible = "mediatek,mt8195-pcie",
+ "mediatek,mt8192-pcie";
+ power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
+
+ #interrupt-cells = <1>;
@@ -1241,6 +1339,34 @@
reg = <0x189 0x2>;
bits = <7 5>;
};
+ pciephy_rx_ln1: pciephy-rx-ln1@190 {
+ reg = <0x190 0x1>;
+ bits = <0 4>;
+ };
+ pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190 {