Re: [PATCH 3/5] ACPI/PCI: Add AER bits #defines for PCIE/PCI-X bridges

[Bjorn Helgaas]

On Thu, Oct 27, 2022 at 11:15:54AM +0800, LeoLiu-oc wrote:
> From: leoliu-oc <leoliu-oc@xxxxxxxxxxx>
> 
> Define PCI Express Advanced Error Reporting Extended Capabilities bits.
> 
> Signed-off-by: leoliu-oc <leoliu-oc@xxxxxxxxxxx>
> ---
>  include/uapi/linux/pci_regs.h | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 57b8e2ffb1dd..3662106fd8dc 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -799,6 +799,11 @@
>  #define  PCI_ERR_ROOT_AER_IRQ		0xf8000000 /* Advanced Error Interrupt Message Number */
>  #define PCI_ERR_ROOT_ERR_SRC	0x34	/* Error Source Identification */
>  
> +/* PCI Express Advanced Error Reporting Extended Capabilities for Bridges */
> +#define PCI_ERR_UNCOR_MASK2		0x30	/* Secondary Uncorrectable Error Mask */
> +#define PCI_ERR_UNCOR_SEVER2	0x34	/* Secondary Uncorrectable Error Severit */
> +#define PCI_ERR_CAP2			0x38	/* Secondary Advanced Error Capabilities */

Can you include a spec reference for these?  I'm looking at PCIe r6.0,
sec 7.8.4, and I don't see anything I can match up with these.

Bjorn