[irqchip: irq/irqchip-next] ACPI / PCI: fix LPIC IRQ model default PCI IRQ polarity

[irqchip-bot for Jianmin Lv]

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID:     d0c50cc4b957b2cf6e43cec4998d212b5abe9220
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/d0c50cc4b957b2cf6e43cec4998d212b5abe9220
Author:        Jianmin Lv <lvjianmin@xxxxxxxxxxx>
AuthorDate:    Sat, 22 Oct 2022 15:59:52 +08:00
Committer:     Marc Zyngier <maz@xxxxxxxxxx>
CommitterDate: Sat, 26 Nov 2022 12:57:18 

ACPI / PCI: fix LPIC IRQ model default PCI IRQ polarity

On LoongArch based systems, the PCI devices (e.g. SATA controllers and
PCI-to-PCI bridge controllers) in Loongson chipsets output high-level
interrupt signal to the interrupt controller they are connected (see
Loongson 7A1000 Bridge User Manual v2.00, sec 5.3, "For the bridge chip,
AC97 DMA interrupts are edge triggered, gpio interrupts can be configured
to be level triggered or edge triggered as needed, and the rest of the
interrupts are level triggered and active high."), while the IRQs are
active low from the perspective of PCI (see Conventional PCI spec r3.0,
sec 2.2.6, "Interrupts on PCI are optional and defined as level sensitive,
asserted low."), which means that the interrupt output of PCI devices plugged
into PCI-to-PCI bridges of Loongson chipset will be also converted to high-level.
So high level triggered type is required to be passed to acpi_register_gsi()
when creating mappings for PCI devices.

Signed-off-by: Jianmin Lv <lvjianmin@xxxxxxxxxxx>
Reviewed-by: Huacai Chen <chenhuacai@xxxxxxxxxxx>
Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20221022075955.11726-2-lvjianmin@xxxxxxxxxxx
---
 drivers/acpi/pci_irq.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c
index 08e1577..ff30cec 100644
--- a/drivers/acpi/pci_irq.c
+++ b/drivers/acpi/pci_irq.c
@@ -387,13 +387,15 @@ int acpi_pci_irq_enable(struct pci_dev *dev)
 	u8 pin;
 	int triggering = ACPI_LEVEL_SENSITIVE;
 	/*
-	 * On ARM systems with the GIC interrupt model, level interrupts
+	 * On ARM systems with the GIC interrupt model, or LoongArch
+	 * systems with the LPIC interrupt model, level interrupts
 	 * are always polarity high by specification; PCI legacy
 	 * IRQs lines are inverted before reaching the interrupt
 	 * controller and must therefore be considered active high
 	 * as default.
 	 */
-	int polarity = acpi_irq_model == ACPI_IRQ_MODEL_GIC ?
+	int polarity = acpi_irq_model == ACPI_IRQ_MODEL_GIC ||
+		       acpi_irq_model == ACPI_IRQ_MODEL_LPIC ?
 				      ACPI_ACTIVE_HIGH : ACPI_ACTIVE_LOW;
 	char *link = NULL;
 	char link_desc[16];