Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree

[Icenowy Zheng]

在 2022-11-27星期日的 17:21 +0000，Conor Dooley写道：
> +CC Icenowy
> 
> On Sun, Nov 27, 2022 at 09:24:45PM +0800, Jisheng Zhang wrote:
> > Add a baisc dtsi for the bouffalolab bl808 SoC.
> > 
> > Signed-off-by: Jisheng Zhang <jszhang@xxxxxxxxxx>
> > ---
> >  arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74
> > ++++++++++++++++++++++
> >  1 file changed, 74 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > 
> > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > new file mode 100644
> > index 000000000000..f4b170ccc32e
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > @@ -0,0 +1,74 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +/*
> > + * Copyright (C) 2022 Jisheng Zhang <jszhang@xxxxxxxxxx>
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > +       compatible = "bouffalolab,bl808";
> > +       #address-cells = <1>;
> > +       #size-cells = <1>;
> > +
> > +       cpus {
> > +               timebase-frequency = <1000000>;
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +
> > +               cpu0: cpu@0 {
> > +                       compatible = "thead,c906", "riscv";
> > +                       device_type = "cpu";
> > +                       reg = <0>;
> > +                       d-cache-block-size = <64>;
> > +                       d-cache-sets = <256>;
> > +                       d-cache-size = <32768>;
> > +                       i-cache-block-size = <64>;
> > +                       i-cache-sets = <128>;
> > +                       i-cache-size = <32768>;
> > +                       mmu-type = "riscv,sv39";
> > +                       riscv,isa = "rv64imafdc";
> > +
> > +                       cpu0_intc: interrupt-controller {
> > +                               compatible = "riscv,cpu-intc";
> > +                               interrupt-controller;
> > +                               #address-cells = <0>;
> > +                               #interrupt-cells = <1>;
> > +                       };
> > +               };
> > +       };
> > +
> > +       xtal: xtal-clk {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               /* This value must be overridden by the board */
> > +               clock-frequency = <0>;
> > +       };
> > +
> > +       soc {
> > +               compatible = "simple-bus";
> > +               ranges;
> > +               interrupt-parent = <&plic>;
> > +               dma-noncoherent;
> > +               #address-cells = <1>;
> > +               #size-cells = <1>;
> > +
> > +               uart0: serial@30002000 {
> > +                       compatible = "bouffalolab,bl808-uart";
> > +                       reg = <0x30002000 0x1000>;
> > +                       interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&xtal>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               plic: interrupt-controller@e0000000 {
> > +                       compatible = "thead,c900-plic";
> 
> Hmm, @Icenowy - should this use your new open-c906-plic compatible
> from
> 20221121041757.418645-4-uwu@xxxxxxxxxx ?

I am against using openc906-plic.

Maybe I will add "thead,c906-plic", "thead,c900-plic" as an valid
compatible, as there seems to be few options related to PLIC/CLINT for
C906/C910 (at least as the open document of them say).

> 
> As is, dtbs_check gives a:
> bl808-sipeed-m1s-dock.dtb: interrupt-controller@e0000000: compatible:
> 'oneOf' conditional failed, one must be fixed:
>         ['thead,c900-plic'] is too short
> 
> > +                       reg = <0xe0000000 0x4000000>;
> > +                       interrupts-extended = <&cpu0_intc
> > 0xffffffff>,
> > +                                             <&cpu0_intc 9>;
> > +                       interrupt-controller;
> > +                       #address-cells = <0>;
> > +                       #interrupt-cells = <2>;
> > +                       riscv,ndev = <64>;
> > +               };
> > +       };
> > +};
> > -- 
> > 2.38.1
> > 
> > 
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