[PATCH] riscv: head: use 0 as the default text_offset

[Jisheng Zhang]

Commit 0f327f2aaad6 ("RISC-V: Add an Image header that boot loader can
parse.") adds an image header which "is based on ARM64 boot image
header and provides an opportunity to combine both ARM64 & RISC-V
image headers in future.". At that time, arm64's default text_offset
is 0x80000, this is to give "512 KB of guaranteed BSS space to put
the swapper page tables" as commit cfa7ede20f13 ("arm64: set TEXT_OFFSET
to 0x0 in preparation for removing it entirely") pointed out, but
riscv doesn't need the space, so use 0 as the default text_offset.

Before this patch, booting linux kernel on Sipeed bl808 M1s Dock
with u-boot booti cmd:
[    0.000000] OF: fdt: Ignoring memory range 0x50000000 - 0x50200000
...
[    0.000000]   DMA32    [mem 0x0000000050200000-0x0000000053ffffff]
As can be seen, 2MB DDR(0x50000000 - 0x501fffff) can't be used by
linux.

After this patch, the 64MB DDR is fully usable by linux
[    0.000000]   DMA32    [mem 0x0000000050000000-0x0000000053ffffff]

Signed-off-by: Jisheng Zhang <jszhang@xxxxxxxxxx>
---
 arch/riscv/kernel/head.S | 12 +-----------
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index b865046e4dbb..ef95943f7a70 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -38,18 +38,8 @@ ENTRY(_start)
 	.word 0
 #endif
 	.balign 8
-#ifdef CONFIG_RISCV_M_MODE
-	/* Image load offset (0MB) from start of RAM for M-mode */
+	/* Image load offset (0MB) from start of RAM */
 	.dword 0
-#else
-#if __riscv_xlen == 64
-	/* Image load offset(2MB) from start of RAM */
-	.dword 0x200000
-#else
-	/* Image load offset(4MB) from start of RAM */
-	.dword 0x400000
-#endif
-#endif
 	/* Effective size of kernel image */
 	.dword _end - _start
 	.dword __HEAD_FLAGS
-- 
2.37.2