[PATCH net v2 2/2] phy: aquantia: Determine rate adaptation support from registers
From: Sean Anderson
Date: Mon Nov 28 2022 - 14:55:32 EST
When autonegotiation completes, the phy interface will be set based on
the global config register for that speed. If the SERDES mode is set to
something which the MAC does not support, then the link will not come
up. To avoid this, validate each combination of interface speed and link
speed which might be configured. This way, we ensure that we only
consider rate adaptation in our advertisement when we can actually use
it.
The API for get_rate_matching requires that PHY_INTERFACE_MODE_NA be
handled properly. To do this, we adopt a structure similar to
phylink_validate. At the top-level, we either validate a particular
interface speed or all of them. Below that, we validate each combination
of serdes speed and link speed.
For some firmwares, not all speeds are supported. In this case, the
global config register for that speed will be initialized to zero
(indicating that rate adaptation is not supported). We can detect this
by reading the PMA/PMD speed register to determine which speeds are
supported. This register is read once in probe and cached for later.
Fixes: 3c42563b3041 ("net: phy: aquantia: Add support for rate matching")
Signed-off-by: Sean Anderson <sean.anderson@xxxxxxxx>
---
This commit should not get backported until it soaks in master for a
while.
The names for the bits in MDIO_SPEED are pretty ugly. IMO
they should all use the MDIO_PMA_SPEED_ prefix, but I think since they
are in uapi we are stuck with these names...
Changes in v2:
- Rework to just validate things instead of modifying registers
drivers/net/phy/aquantia_main.c | 156 ++++++++++++++++++++++++++++++--
1 file changed, 150 insertions(+), 6 deletions(-)
diff --git a/drivers/net/phy/aquantia_main.c b/drivers/net/phy/aquantia_main.c
index 47a76df36b74..998cdbb59ae3 100644
--- a/drivers/net/phy/aquantia_main.c
+++ b/drivers/net/phy/aquantia_main.c
@@ -109,6 +109,12 @@
#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
+#define VEND1_GLOBAL_CFG_SERDES_MODE GENMASK(2, 0)
+#define VEND1_GLOBAL_CFG_SERDES_MODE_XFI 0
+#define VEND1_GLOBAL_CFG_SERDES_MODE_SGMII 3
+#define VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII 4
+#define VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G 6
+#define VEND1_GLOBAL_CFG_SERDES_MODE_XFI20G 7
#define VEND1_GLOBAL_RSVD_STAT1 0xc885
#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
@@ -173,6 +179,7 @@ static const struct aqr107_hw_stat aqr107_hw_stats[] = {
struct aqr107_priv {
u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
+ int supported_speeds;
};
static int aqr107_get_sset_count(struct phy_device *phydev)
@@ -675,13 +682,141 @@ static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
return 0;
}
+/**
+ * aqr107_rate_adapt_ok_one() - Validate rate adaptation for one configuration
+ * @phydev: The phy to act on
+ * @serdes_speed: The speed of the serdes (aka the phy interface)
+ * @link_speed: The speed of the link
+ *
+ * This function validates whether rate adaptation will work for a particular
+ * combination of @serdes_speed and @link_speed.
+ *
+ * Return: %true if the global config register for @link_speed is configured for
+ * rate adaptation, %true if @link_speed will not be advertised, %false
+ * otherwise.
+ */
+static bool aqr107_rate_adapt_ok_one(struct phy_device *phydev, int serdes_speed,
+ int link_speed)
+{
+ struct aqr107_priv *priv = phydev->priv;
+ int val, speed_bit;
+ u32 reg;
+
+ phydev_dbg(phydev, "validating link_speed=%d serdes_speed=%d\n",
+ link_speed, serdes_speed);
+
+ switch (link_speed) {
+ case SPEED_10000:
+ reg = VEND1_GLOBAL_CFG_10G;
+ speed_bit = MDIO_SPEED_10G;
+ break;
+ case SPEED_5000:
+ reg = VEND1_GLOBAL_CFG_5G;
+ speed_bit = MDIO_PCS_SPEED_5G;
+ break;
+ case SPEED_2500:
+ reg = VEND1_GLOBAL_CFG_2_5G;
+ speed_bit = MDIO_PCS_SPEED_2_5G;
+ break;
+ case SPEED_1000:
+ reg = VEND1_GLOBAL_CFG_1G;
+ speed_bit = MDIO_PMA_SPEED_1000;
+ break;
+ case SPEED_100:
+ reg = VEND1_GLOBAL_CFG_100M;
+ speed_bit = MDIO_PMA_SPEED_100;
+ break;
+ case SPEED_10:
+ reg = VEND1_GLOBAL_CFG_10M;
+ speed_bit = MDIO_PMA_SPEED_10;
+ break;
+ default:
+ WARN_ON_ONCE(1);
+ return false;
+ }
+
+ /* Vacuously OK, since we won't advertise it anyway */
+ if (!(priv->supported_speeds & speed_bit))
+ return true;
+
+ val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
+ if (val < 0) {
+ phydev_warn(phydev, "could not read register %x:%.04x (err = %d)\n",
+ MDIO_MMD_VEND1, reg, val);
+ return false;
+ }
+
+ phydev_dbg(phydev, "%x:%.04x = %.04x\n", MDIO_MMD_VEND1, reg, val);
+ if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) !=
+ VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
+ return false;
+
+ switch (FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val)) {
+ case VEND1_GLOBAL_CFG_SERDES_MODE_XFI20G:
+ return serdes_speed == SPEED_20000;
+ case VEND1_GLOBAL_CFG_SERDES_MODE_XFI:
+ return serdes_speed == SPEED_10000;
+ case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G:
+ return serdes_speed == SPEED_5000;
+ case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII:
+ return serdes_speed == SPEED_2500;
+ case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII:
+ return serdes_speed == SPEED_1000;
+ default:
+ return false;
+ }
+}
+
+/**
+ * aqr107_rate_adapt_ok() - Validate rate adaptation for an interface speed
+ * @phydev: The phy device
+ * @speed: The serdes (phy interface) speed
+ *
+ * This validates whether rate adaptation will work for a particular @speed.
+ * All link speeds less than or equal to @speed are validate to ensure they are
+ * configured properly.
+ *
+ * Return: %true if rate adaptation is supported for @speed, %false otherwise.
+ */
+static bool aqr107_rate_adapt_ok(struct phy_device *phydev, int speed)
+{
+ switch (speed) {
+ case SPEED_10000:
+ if (!aqr107_rate_adapt_ok_one(phydev, speed, SPEED_10000) ||
+ !aqr107_rate_adapt_ok_one(phydev, speed, SPEED_5000))
+ return false;
+ fallthrough;
+ case SPEED_2500:
+ if (!aqr107_rate_adapt_ok_one(phydev, speed, SPEED_2500))
+ return false;
+ fallthrough;
+ case SPEED_1000:
+ if (!aqr107_rate_adapt_ok_one(phydev, speed, SPEED_1000) ||
+ !aqr107_rate_adapt_ok_one(phydev, speed, SPEED_100) ||
+ !aqr107_rate_adapt_ok_one(phydev, speed, SPEED_10))
+ return false;
+ return true;
+ default:
+ return false;
+ };
+}
+
static int aqr107_get_rate_matching(struct phy_device *phydev,
phy_interface_t iface)
{
- if (iface == PHY_INTERFACE_MODE_10GBASER ||
- iface == PHY_INTERFACE_MODE_2500BASEX ||
- iface == PHY_INTERFACE_MODE_NA)
+ if (iface != PHY_INTERFACE_MODE_NA) {
+ if (aqr107_rate_adapt_ok(phydev,
+ phy_interface_max_speed(iface)))
+ return RATE_MATCH_PAUSE;
+ else
+ return RATE_MATCH_NONE;
+ }
+
+ if (aqr107_rate_adapt_ok(phydev, SPEED_10000) ||
+ aqr107_rate_adapt_ok(phydev, SPEED_2500) ||
+ aqr107_rate_adapt_ok(phydev, SPEED_1000))
return RATE_MATCH_PAUSE;
+
return RATE_MATCH_NONE;
}
@@ -711,10 +846,19 @@ static int aqr107_resume(struct phy_device *phydev)
static int aqr107_probe(struct phy_device *phydev)
{
- phydev->priv = devm_kzalloc(&phydev->mdio.dev,
- sizeof(struct aqr107_priv), GFP_KERNEL);
- if (!phydev->priv)
+ struct aqr107_priv *priv;
+
+ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
return -ENOMEM;
+ phydev->priv = priv;
+
+ priv->supported_speeds = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
+ MDIO_SPEED);
+ if (priv->supported_speeds < 0) {
+ phydev_err(phydev, "could not determine supported speeds\n");
+ return priv->supported_speeds;
+ };
return aqr_hwmon_probe(phydev);
}
--
2.35.1.1320.gc452695387.dirty