Re: [PATCH v2 3/4] ARM: dts: armada-38x: Fix compatible string for gpios

[Chris Packham]

Hi Pali,

On 15/07/22 06:33, Pali Rohár wrote:
> Armada 38x supports per CPU interrupts for gpios, like Armada XP. Pre-XP
> variants like Armada 370 do not support per CPU interrupts for gpios.
>
> So change compatible string for Armada 38x from "marvell,armada-370-gpio"
> which indicates pre-XP variant to "marvell,armadaxp-gpio" which indicates
> XP variant or new.
>
> Driver gpio-mvebu.c which handles both pre-XP and XP variants already
> provides support for per CPU interrupts on XP and newer variants.
>
> Signed-off-by: Pali Rohár <pali@xxxxxxxxxx>
> Fixes: 7cb2acb3fbae ("ARM: dts: mvebu: Add PWM properties for armada-38x")
> ---
>   arch/arm/boot/dts/armada-38x.dtsi | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
> index df3c8d1d8f64..9343de6947b3 100644
> --- a/arch/arm/boot/dts/armada-38x.dtsi
> +++ b/arch/arm/boot/dts/armada-38x.dtsi
> @@ -292,7 +292,7 @@
>   			};
>   
>   			gpio0: gpio@18100 {
> -				compatible = "marvell,armada-370-gpio",
> +				compatible = "marvell,armadaxp-gpio",
>   					     "marvell,orion-gpio";
>   				reg = <0x18100 0x40>, <0x181c0 0x08>;
>   				reg-names = "gpio", "pwm";

Currently when you specify the "marvell,armadaxp-gpio" compatible this 
causes the driver to expect the 2nd reg property to be the per-CPU 
interrupt registers. The code in question is

         /*
          * The Armada XP has a second range of registers for the
          * per-CPU registers
          */
         if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
                 base = devm_platform_ioremap_resource(pdev, 1);
                 if (IS_ERR(base))
                         return PTR_ERR(base);

                 mvchip->percpu_regs =
                         devm_regmap_init_mmio(&pdev->dev, base,
&mvebu_gpio_regmap_config);
                 if (IS_ERR(mvchip->percpu_regs))
                         return PTR_ERR(mvchip->percpu_regs);
         }

But with your code change resource[1] is pointing at the blink enable 
register not at the per-CPU interrupt register (offset 18800/18840).


> @@ -310,7 +310,7 @@
>   			};
>   
>   			gpio1: gpio@18140 {
> -				compatible = "marvell,armada-370-gpio",
> +				compatible = "marvell,armadaxp-gpio",
>   					     "marvell,orion-gpio";
>   				reg = <0x18140 0x40>, <0x181c8 0x08>;
>   				reg-names = "gpio", "pwm";