Re: [PATCH] Implement ioremap_prot support (v2)

From: Palmer Dabbelt
Date: Fri Dec 02 2022 - 10:00:00 EST


On Fri, 02 Dec 2022 00:33:56 PST (-0800), jiangjianwen@xxxxxxxxxxxxx wrote:
Feature ioremap_prot only needs an implementation of pte_pgprot on riscv.
That macro is similar to the same one on platform loongarch, mips and sh.
We just need:
1. replace _PFN_MASK with _PAGE_PFN_MASK in pte_gpprot;
2. add "select HAVE_IOREMAP_PROT" into arch/riscv/Kconfig;
3. add "depends on MMU" into drivers/fpga/Kconfig to fix the building error "undefined reference to generic_access_phys".

That third one should be its own patch, it's not really related to the RISC-V bits.


Signed-off-by: Jianwen Jiang <jiangjianwen@xxxxxxxxxxxxx>
---
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/page.h | 2 ++
drivers/fpga/Kconfig | 1 +
3 files changed, 4 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fa78595a6089..5ed2c7361040 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -95,6 +95,7 @@ config RISCV
select HAVE_FUNCTION_ERROR_INJECTION
select HAVE_GCC_PLUGINS
select HAVE_GENERIC_VDSO if MMU && 64BIT
+ select HAVE_IOREMAP_PROT
select HAVE_IRQ_TIME_ACCOUNTING
select HAVE_KPROBES if !XIP_KERNEL
select HAVE_KPROBES_ON_FTRACE if !XIP_KERNEL
diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
index ac70b0fd9a9a..cb08a4911d60 100644
--- a/arch/riscv/include/asm/page.h
+++ b/arch/riscv/include/asm/page.h
@@ -84,6 +84,8 @@ typedef struct page *pgtable_t;
#define __pgd(x) ((pgd_t) { (x) })
#define __pgprot(x) ((pgprot_t) { (x) })

+#define pte_pgprot(x) __pgprot(pte_val(x) & ~_PAGE_PFN_MASK)
+
#ifdef CONFIG_64BIT
#define PTE_FMT "%016lx"
#else
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index bbe0a7cabb75..0493272b8bff 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -5,6 +5,7 @@

menuconfig FPGA
tristate "FPGA Configuration Framework"
+ depends on MMU
help
Say Y here if you want support for configuring FPGAs from the
kernel. The FPGA framework adds an FPGA manager class and FPGA