[tip: x86/cpu] x86/pat: Handle TDX guest PAT initialization

[tip-bot2 for Juergen Gross]

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     c11ca45441d56ed6d353548cad660e04f0b6605d
Gitweb:        https://git.kernel.org/tip/c11ca45441d56ed6d353548cad660e04f0b6605d
Author:        Juergen Gross <jgross@xxxxxxxx>
AuthorDate:    Mon, 05 Dec 2022 09:04:32 +01:00
Committer:     Borislav Petkov (AMD) <bp@xxxxxxxxx>
CommitterDate: Mon, 05 Dec 2022 11:03:27 +01:00

x86/pat: Handle TDX guest PAT initialization

With the decoupling of PAT and MTRR initialization, PAT will be used
even with MTRRs disabled. This seems to break booting up as TDX guest,
as the recommended sequence to set the PAT MSR across CPUs can't work
in TDX guests due to disabling caches via setting CR0.CD isn't allowed
in TDX mode.

This is an inconsistency in the Intel documentation between the SDM
and the TDX specification. For now handle TDX mode the same way as Xen
PV guest mode by just accepting the current PAT MSR setting without
trying to modify it.

  [ bp: Align conditions for better readability. ]

Signed-off-by: Juergen Gross <jgross@xxxxxxxx>
Signed-off-by: Borislav Petkov (AMD) <bp@xxxxxxxxx>
Link: https://lore.kernel.org/r/20221205080433.16643-2-jgross@xxxxxxxx
---
 arch/x86/mm/pat/memtype.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/x86/mm/pat/memtype.c b/arch/x86/mm/pat/memtype.c
index 9aab17d..46de9cf 100644
--- a/arch/x86/mm/pat/memtype.c
+++ b/arch/x86/mm/pat/memtype.c
@@ -296,8 +296,13 @@ void __init pat_bp_init(void)
 	/*
 	 * Xen PV doesn't allow to set PAT MSR, but all cache modes are
 	 * supported.
+	 * When running as TDX guest setting the PAT MSR won't work either
+	 * due to the requirement to set CR0.CD when doing so. Rely on
+	 * firmware to have set the PAT MSR correctly.
 	 */
-	if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV)) {
+	if (pat_disabled ||
+	    cpu_feature_enabled(X86_FEATURE_XENPV) ||
+	    cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) {
 		init_cache_modes(pat_msr_val);
 		return;
 	}