Hi Angelo,
On Mon, 2022-12-05 at 15:21 +0100, AngeloGioacchino Del Regno wrote:
Il 05/12/22 07:57, Xiangsheng Hou ha scritto:
Add ECC support fot MT7986 IC.
Signed-off-by: Xiangsheng Hou <xiangsheng.hou@xxxxxxxxxxxx>
---
drivers/mtd/nand/ecc-mtk.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/mtd/nand/ecc-mtk.c b/drivers/mtd/nand/ecc-
mtk.c
index 9f9b201fe706..c2f6cfa76a04 100644
--- a/drivers/mtd/nand/ecc-mtk.c
+++ b/drivers/mtd/nand/ecc-mtk.c
@@ -79,6 +79,10 @@ static const u8 ecc_strength_mt7622[] = {
4, 6, 8, 10, 12
};
+static const u8 ecc_strength_mt7986[] = {
+ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24
+};
+
enum mtk_ecc_regs {
ECC_ENCPAR00,
ECC_ENCIRQ_EN,
@@ -483,6 +487,17 @@ static const struct mtk_ecc_caps
mtk_ecc_caps_mt7622 = {
.pg_irq_sel = 0,
};
+static const struct mtk_ecc_caps mtk_ecc_caps_mt7986 = {
+ .err_mask = 0x1f,
Can't we use GENMASK() to define err_mask instead?
#define MT7986_ERRNUM GENMASK(4, 0)
P.S.: Did I get that right? Is that referred to the ERRNUM(x) bits
Yes, you are right.
I will change like
#define ECC_ERRMASK(x) GENMASK(x, 0),
since other IC driver data will use 0x3f and 0x7f err_mask.