[PATCH] irqchip/gic-v3-its: remove the shareability of ITS

[Harry Song]

I know this is a very wrong patch, but my platform
has an abnormal ITS problem caused by data consistency:
My chip does not support Cache Coherent Interconnect (CCI).
By default, ITS driver is the inner memory attribute.
gits_write_cbaser() is used to write the inner memory
attribute. But hw doesn't return the hardware's non-shareable
property,so I don't think reading GITS_CBASER and GICR_PROPBASER
here will get the real property of the current hardware: inner
or outer shareable is not supported, so I would like to know
whether ITS driver cannot be used on chips without CCI, or
what method can be used to use ITS driver on chips without CCI?

The current patch is designed to make ITS think that the current
chip has no inner or outer memory properties, and then use
its by flushing dcache.

This is the log for bug reports without patches:

[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000003460000
[    0.000000] ITS [mem 0x03440000-0x0345ffff]
[    0.000000] ITS@0x0000000003440000: allocated 8192 Devices @41850000 (indirect, esz 8, psz 64K, shr 0)
[    0.000000] ITS@0x0000000003440000: allocated 32768 Interrupt Collections @41860000 (flat, esz 2, psz 64K, shr 0)
[    0.000000] GICv3: using LPI property table @0x0000000041870000
[    0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000041880000
[    0.000000] ITS queue timeout (64 1)
[    0.000000] ITS cmd its_build_mapc_cmd failed
[    0.000000] ITS queue timeout (128 1)
[    0.000000] ITS cmd its_build_invall_cmd failed

Signed-off-by: Harry Song <jundongsong1@xxxxxxxxx>
---

I am very sorry to bother you. This problem has been bothering me for several weeks.
I am looking forward to your reply.

Thanks,
Harry

 drivers/irqchip/irq-gic-v3-its.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 973ede019..780099ce2 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2359,6 +2359,11 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
 	its_write_baser(its, baser, val);
 	tmp = baser->val;
 
+	if (tmp & GITS_BASER_SHAREABILITY_MASK)
+		tmp &= ~GITS_BASER_SHAREABILITY_MASK;
+	else
+		gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
+
 	if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
 		/*
 		 * Shareability didn't stick. Just use
@@ -3096,6 +3101,8 @@ static void its_cpu_init_lpis(void)
 	gicr_write_propbaser(val, rbase + GICR_PROPBASER);
 	tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
 
+	tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
+
 	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
 		if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
 			/*
@@ -5095,6 +5102,8 @@ static int __init its_probe_one(struct resource *res,
 	gits_write_cbaser(baser, its->base + GITS_CBASER);
 	tmp = gits_read_cbaser(its->base + GITS_CBASER);
 
+	tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
+
 	if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
 		if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
 			/*
-- 
2.25.1