Re: [PATCH kernel 3/3] x86/sev: Do not handle #VC for DR7 read/write

[Alexey Kardashevskiy]

On 8/12/22 06:07, Sean Christopherson wrote:
> On Wed, Dec 07, 2022, Borislav Petkov wrote:
> > On Thu, Dec 01, 2022 at 05:38:33PM +0000, Sean Christopherson wrote:
> > > Probably high time to add a helper/macro to convert the SEV_STATUS to
> > > the SEV_FEATURES field.
> >
> > Nah, there's a couple of
> >
> > MSR_AMD64_SEV*
> >
> > defines in arch/x86/include/asm/msr-index.h.
> >
> > Bit 5 should simply be added there.
>
> Ah, yeah, that's much better.

Sorry, I am not following. How is moving the bit makes 
SEV_STATUS_TO_FEATURES() not needed?

When I am setting it in VMSA SEV_FEATURES - it is a bit 5.

Inside a SEV VM, it is SEV_STATUS MSR and there it is bit 7. Mentioned 
MSR_AMD64_SEV* are SEV_STATUS MSR bits.

Since the current patch is bad, I'd rather define the bit twice then:

arch/x86/include/asm/msr-index.h:
#define MSR_AMD64_SEV_FEAT_DEBUG_SWAP    BIT_ULL(7)

arch/x86/include/asm/svm.h
#define SVM_SEV_FEAT_DEBUG_SWAP         BIT(5)

as nothing really says that SEV_FEATURES is always going to be 
SEV_STATUS>>2, even though it is now.

Soooo what is acceptable solution here? Thanks,


--
Alexey