[PATCH] pwm: xilinx: Fix overflow issue in 32-bit width PWM mode.

[Kenneth Sloat]

This timer HW supports 8, 16 and 32-bit timer widths. This
driver uses a u32 to store the max value of the timer.
Because addition is done to this max value, when operating
in 32-bit mode, this will result in overflow that makes it
impossible to set the timer period and thus the PWM itself.

To fix this, simply make max a u64. This was tested on a
Zynq UltraScale+.

Signed-off-by: Ken Sloat <ksloat@xxxxxxxxxxxxxxxx>
---
 include/clocksource/timer-xilinx.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/clocksource/timer-xilinx.h b/include/clocksource/timer-xilinx.h
index c0f56fe6d22a..d116f18de899 100644
--- a/include/clocksource/timer-xilinx.h
+++ b/include/clocksource/timer-xilinx.h
@@ -41,7 +41,7 @@ struct regmap;
 struct xilinx_timer_priv {
 	struct regmap *map;
 	struct clk *clk;
-	u32 max;
+	u64 max;
 };
 
 /**
-- 
2.17.1