Re: [PATCH 2/4] arm64: dts: qcom: sm6125: Add UFS nodes

[Krzysztof Kozlowski]

On 14/12/2022 10:32, Lux Aliaga wrote:
> This commit adds a UFS host controller node and its corresponding PHY to

Do not use "This commit/patch".
https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95

> the sm6125 platform.
> 
> Signed-off-by: Lux Aliaga <they@xxxxxxxxx>

You need to thread your patches. git send-email does it automatically.
The patchset is now difficult to review and not possible to apply
because of broken thread.

> ---
>  arch/arm64/boot/dts/qcom/sm6125.dtsi | 70 ++++++++++++++++++++++++++++
>  1 file changed, 70 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> index 1fe3fa3ad877..f43b005b9454 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> @@ -506,6 +506,76 @@ sdhc_2: mmc@4784000 {
>  			status = "disabled";
>  		};
>  
> +		ufs_mem_hc: ufshc@4804000 {

Node name just "ufs"

> +			compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
> +			reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
> +			reg-names = "std", "ice";
> +			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> +			phys = <&ufs_mem_phy_lanes>;
> +			phy-names = "ufsphy";
> +			lanes-per-direction = <1>;
> +			#reset-cells = <1>;
> +			resets = <&gcc GCC_UFS_PHY_BCR>;
> +			reset-names = "rst";
> +
> +			clock-names =
> +				"core_clk",

Merge these two lines.
> +				"bus_aggr_clk",
> +				"iface_clk",
> +				"core_clk_unipro",
> +				"core_clk_ice",
> +				"ref_clk",
> +				"tx_lane0_sync_clk",
> +				"rx_lane0_sync_clk";
> +			clocks =
> +				<&gcc GCC_UFS_PHY_AXI_CLK>, // 200m

Ditto and drop the comment - I don't get to what 200m refers to.

> +				<&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, // 200m

Drop this comment as well and all others.

> +				<&gcc GCC_UFS_PHY_AHB_CLK>, // 0
> +				<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, // 150m
> +				<&gcc GCC_UFS_PHY_ICE_CORE_CLK>, // 300m
> +				<&rpmcc RPM_SMD_XO_CLK_SRC>, // 19.2m
> +				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, // 0
> +				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; // 0
> +
> +			freq-table-hz =
> +				<50000000 240000000>,

Merge lines.

> +				<0 0>,
> +				<0 0>,
> +				<37500000 150000000>,
> +				<75000000 300000000>,
> +				<0 0>,
> +				<0 0>,
> +				<0 0>;
> +
> +			non-removable;

Just to be sure - does your DTS change pass dtbs_check?

> +			status = "disabled";
> +		};
> +
> +		ufs_mem_phy: phy@4807000 {
> +			compatible = "qcom,sm6115-qmp-ufs-phy";

Most likely this needs also dedicated compatible.

> +			reg = <0x04807000 0x1c4>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			power-domains = <&gcc UFS_PHY_GDSC>;
> +
> +			clock-names = "ref", "ref_aux";
> +			clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
> +					 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> +
> +			resets = <&ufs_mem_hc 0>;
> +			reset-names = "ufsphy";
> +			status = "disabled";
> +
> +			ufs_mem_phy_lanes: lanes@4807400 {
> +				reg = <0x4807400 0x098>,
> +				      <0x4807600 0x130>,
> +				      <0x4807c00 0x16c>;
> +				#phy-cells = <0>;
> +			};
> +		};
> +
>  		usb3: usb@4ef8800 {
>  			compatible = "qcom,sm6125-dwc3", "qcom,dwc3";
>  			reg = <0x04ef8800 0x400>;

Best regards,
Krzysztof